By: Foo_ (foo.delete@this.nomail.com), May 18, 2021 1:58 am
Room: Moderated Discussions
Little Horn (sink.delete@this.example.net) on May 17, 2021 5:03 pm wrote:
> Thoughts?
It looks like they are hand-waving a lot of the difficulties.
- storing lots of thread state in registers in the CPU is supposed to be cheap (they also limit their size estimate to SSE3, conveniently ignoring AVX and AVX512)
- software scheduling still needs to happen in the not unlikely event that the total number of threads managed by software is larger than the number of HW theads (not unlikely, because they are advocating for the use of the blocking IO model, which requires one thread per on-going request)
- cache and TLB flushes will still happen... but, according to the authors, it's not a problem because it's not worse. Yet avoiding the *cost* of context switches was the entire motivation for their proposal
> Thoughts?
It looks like they are hand-waving a lot of the difficulties.
- storing lots of thread state in registers in the CPU is supposed to be cheap (they also limit their size estimate to SSE3, conveniently ignoring AVX and AVX512)
- software scheduling still needs to happen in the not unlikely event that the total number of threads managed by software is larger than the number of HW theads (not unlikely, because they are advocating for the use of the blocking IO model, which requires one thread per on-going request)
- cache and TLB flushes will still happen... but, according to the authors, it's not a problem because it's not worse. Yet avoiding the *cost* of context switches was the entire motivation for their proposal