By: Adrian (a.delete@this.acm.org), May 27, 2021 11:13 pm
Room: Moderated Discussions
Paul A. Clayton (paaronclayton.delete@this.gmail.com) on May 27, 2021 12:00 pm wrote:
>
> As a multithreading bigot, I am disappointed that no multithreading is supported. With relatively lower
> performance (smaller) cores, more cores may be a better choice, especially with a more limited design budget.
> Such may also be more attractive to smaller customers as it avoids the pressure to tune yet one more knob
> (and restrict sharing with respect to side channels as well as communicate such complexities to customers).
> I think well-designed multithreading support provides useful configurability, but I also have affection
> for heterogeneous multiprocessors, non-uniform cache access, and other quirky features.
In an interview,
https://www.nextplatform.com/2021/05/24/the-ampere-arm-server-chip-roadmap-may-lead-beyond-hyperscalers/
they have said that a differentiating point against competition in their future custom cores will be better isolation between threads.
So given this design target, it is clear that even in their future cores they will not use any kind of SMT and they will also not increase cache sharing in any way, but they might decrease it.
Sharing resources is good for improving the average throughput, but when security is valued above efficiency, then sharing has to be avoided, and this appears to be Ampere's choice, in order to not confront directly AMD.
>
> As a multithreading bigot, I am disappointed that no multithreading is supported. With relatively lower
> performance (smaller) cores, more cores may be a better choice, especially with a more limited design budget.
> Such may also be more attractive to smaller customers as it avoids the pressure to tune yet one more knob
> (and restrict sharing with respect to side channels as well as communicate such complexities to customers).
> I think well-designed multithreading support provides useful configurability, but I also have affection
> for heterogeneous multiprocessors, non-uniform cache access, and other quirky features.
In an interview,
https://www.nextplatform.com/2021/05/24/the-ampere-arm-server-chip-roadmap-may-lead-beyond-hyperscalers/
they have said that a differentiating point against competition in their future custom cores will be better isolation between threads.
So given this design target, it is clear that even in their future cores they will not use any kind of SMT and they will also not increase cache sharing in any way, but they might decrease it.
Sharing resources is good for improving the average throughput, but when security is valued above efficiency, then sharing has to be avoided, and this appears to be Ampere's choice, in order to not confront directly AMD.
| Topic | Posted By | Date |
|---|---|---|
| Ampere Altra Max 16MB LLC with 128 cores | Ganon | 2021/05/25 01:30 AM |
| Ampere Altra Max 16MB LLC with 128 cores | anon | 2021/05/25 03:11 AM |
| Ampere Altra Max 16MB LLC with 128 cores | Heikki Kultala | 2021/05/25 11:22 PM |
| Ampere Altra Max 16MB LLC with 128 cores | Anon | 2021/05/26 01:36 PM |
| Ampere Altra Max 16MB LLC with 128 cores | Chester | 2021/05/26 02:54 PM |
| Ampere Altra Max 16MB LLC with 128 cores | Chester | 2021/05/26 03:03 PM |
| Ampere Altra Max 16MB LLC with 128 cores | Doug S | 2021/05/25 07:50 AM |
| Ampere Altra Max 16MB LLC with 128 cores | Andrei F | 2021/05/25 08:06 AM |
| Ampere Altra Max 16MB LLC with 128 cores | Rayla | 2021/05/25 08:17 AM |
| A few thoughts on Ampere's Altra Max | Paul A. Clayton | 2021/05/27 12:00 PM |
| A few thoughts on Ampere's Altra Max | Björn Ragnar Björnsson | 2021/05/27 03:47 PM |
| Yeah, I should have looked for and through a data sheet (NT) | Paul A. Clayton | 2021/05/27 06:25 PM |
| A few thoughts on Ampere's Altra Max | Adrian | 2021/05/27 11:13 PM |
| Boring can be profitable | Paul A. Clayton | 2021/05/29 12:18 PM |