By: anonymous2 (anonymous2.delete@this.example.com), June 28, 2021 1:54 pm
Room: Moderated Discussions
White Paper: Performance Monitoring Impact of Intel® Transactional Synchronization Extension Memory Ordering Issue
References:
https://hardware.slashdot.org/story/21/06/28/205240/intel-to-disable-tsx-by-default-on-more-cpus-with-new-microcode
https://www.phoronix.com/scan.php?page=news_item&px=Intel-TSX-Off-New-Microcode
This whitepaper describes Intel® Transactional Synchronization Extension
(Intel® TSX) and Performance Monitoring Unit (PMU) behavior due to the
updated microcode for Intel® Xeon® D (code name Skylake-D), Intel® Xeon®
Scalable Processor, and certain Intel® Xeon® Processor E3 v5 and v6 Family
(code name Skylake and Kaby Lake) and 6th, 7th, and 8th Generation Intel®
Core™ i7 and i5 (code name Skylake, Kaby Lake, Coffee Lake, and Whiskey
Lake)
References:
https://hardware.slashdot.org/story/21/06/28/205240/intel-to-disable-tsx-by-default-on-more-cpus-with-new-microcode
https://www.phoronix.com/scan.php?page=news_item&px=Intel-TSX-Off-New-Microcode
Topic | Posted By | Date |
---|---|---|
Intel to disable TSX on (more) CPUs | anonymous2 | 2021/06/28 01:54 PM |
TSX now disabled on more CPUs | anonymou5 | 2021/06/29 04:51 AM |