Introducing the Scalable Matrix Extension for the Armv9-A Architecture

I noticed ARM have issued yet another of their planned future architecture blogs, this one is called "Scalable Matrix Extension". Same sort of idea as what Intel is implementing as far as I can see. Except there is a strange aspect in that it requires a new mode for SVE called "Streaming mode" SVE. They talk about having the new SME instructons and a significant subset of the existing SVE2 instructions. And they say that one could have a longer length for the registers in streaming and non-streaming mode. As far as I can make out in fact only very straightforward operations are included in streaming mode.

I guess that instead of being 'RISC' instructions these would have a loop dealing with widths greater than the hardware SVE register or memory or cache width. Thy've implemented something like this in the Cortex-M Helium extension, but I'd have thought they could just rely on OoO for the larger application processor If it is so they can have larger tiles in their matrix multiplicatin I'd have thought there would be other tricks that could do the job without a new mode. However I can't see they would have put in a new mode without it being very important to them. Am I missing something?