By: David Kanter (dkanter.delete@this.realworldtech.com), August 4, 2021 8:53 am
Room: Moderated Discussions
Heikki Kultala (heikki.kulta.la.delete@this.gmail.com) on July 30, 2021 2:33 pm wrote:
> --- (---.delete@this.redheron.com) on July 30, 2021 9:38 am wrote:
> > Heikki Kultala (heikki.kult.ala.delete@this.gmail.com) on July 29, 2021 11:18 pm wrote:
> > > Doug S (foo.delete@this.bar.bar) on July 29, 2021 5:44 pm wrote:
> > > > None of it really matters, since the process names have nothing to do with a physical dimension
> > > > anywhere in the design. It is just a placeholder for "2x the transistors in the next generation"
> > > > but we aren't even seeing that lately as TSMC only got 1.8x scaling on N5 and 1.7x on N3
> > > > - but TSMC wasn't calling those 5nm and 3nm, it is mostly outsiders doing so (maybe TSMC
> > > > does as well, but probably only because outsiders referred to them that way)
> > > >
> > > > Who knows what TSMC will call the stuff below N2, will it be N1.4 or P1400 or just
> > > > choose another letter at random, multiply by 10, so X14 then X10 and so on.
> > >
> > > TSMC did not get 1.8x scaling on N5. In reality (by synthesizing any
> > > reasonable piece of logic than does something) it's much worse.
> > >
> > > Or, lets say that TSMC might have gotten 1.8x for single best-case standard cell
> > > component type for their marketing materials, but TSMCs customers get MUCH LESS
> > > than 1,8x for their real-world designs that actually do something useful.
> >
> > Can you provide evidence for this?
>
> No, because the evidence is all under NDA. I've seen
>
> 1) slides containing die area numbers of big licencable IP blocks from a big IP company, same IP
> blocks for "7nm" and "5nm". Those numbers were given to tell how big the IP blocks are. But I did
> the division calculation between the "7nm" and "5nm" numbers and they were far from 1.8x
>
> 2) actual/all synthesis results of some more custom stuff, same logic synthesized to both "7nm" and "5nm".
>
> > The only customers I know of for N5 right now are Apple and Kirin 9000.
>
> TSMC has LOTS of customers for their "5nm" process. Most of the chips just are not available yet.
>
> Tapeout typically happens over a year before the chip is available for sale, and the are is fixed then.
> And practically, synthesis with area estimates that are very close to the final arrive much earlier.
I want to echo what Heikki is saying.
Shrinking is extremely non-uniform.
SRAM is different than logic.
High-density SRAM is different than high-performance SRAM.
The former is single-fin devices, the latter will use some two-fin devices.
Analog is totally different and driven by other factors like passives. Intel 14nm really shrank analog quite a bit.
Additionally, not all customers care equally about area. If you are doing a low-volume ASIC, optimizing area may not make sense compared to reducing the design cost.
All foundry/fab numbers are probably best case.
David
> --- (---.delete@this.redheron.com) on July 30, 2021 9:38 am wrote:
> > Heikki Kultala (heikki.kult.ala.delete@this.gmail.com) on July 29, 2021 11:18 pm wrote:
> > > Doug S (foo.delete@this.bar.bar) on July 29, 2021 5:44 pm wrote:
> > > > None of it really matters, since the process names have nothing to do with a physical dimension
> > > > anywhere in the design. It is just a placeholder for "2x the transistors in the next generation"
> > > > but we aren't even seeing that lately as TSMC only got 1.8x scaling on N5 and 1.7x on N3
> > > > - but TSMC wasn't calling those 5nm and 3nm, it is mostly outsiders doing so (maybe TSMC
> > > > does as well, but probably only because outsiders referred to them that way)
> > > >
> > > > Who knows what TSMC will call the stuff below N2, will it be N1.4 or P1400 or just
> > > > choose another letter at random, multiply by 10, so X14 then X10 and so on.
> > >
> > > TSMC did not get 1.8x scaling on N5. In reality (by synthesizing any
> > > reasonable piece of logic than does something) it's much worse.
> > >
> > > Or, lets say that TSMC might have gotten 1.8x for single best-case standard cell
> > > component type for their marketing materials, but TSMCs customers get MUCH LESS
> > > than 1,8x for their real-world designs that actually do something useful.
> >
> > Can you provide evidence for this?
>
> No, because the evidence is all under NDA. I've seen
>
> 1) slides containing die area numbers of big licencable IP blocks from a big IP company, same IP
> blocks for "7nm" and "5nm". Those numbers were given to tell how big the IP blocks are. But I did
> the division calculation between the "7nm" and "5nm" numbers and they were far from 1.8x
>
> 2) actual/all synthesis results of some more custom stuff, same logic synthesized to both "7nm" and "5nm".
>
> > The only customers I know of for N5 right now are Apple and Kirin 9000.
>
> TSMC has LOTS of customers for their "5nm" process. Most of the chips just are not available yet.
>
> Tapeout typically happens over a year before the chip is available for sale, and the are is fixed then.
> And practically, synthesis with area estimates that are very close to the final arrive much earlier.
I want to echo what Heikki is saying.
Shrinking is extremely non-uniform.
SRAM is different than logic.
High-density SRAM is different than high-performance SRAM.
The former is single-fin devices, the latter will use some two-fin devices.
Analog is totally different and driven by other factors like passives. Intel 14nm really shrank analog quite a bit.
Additionally, not all customers care equally about area. If you are doing a low-volume ASIC, optimizing area may not make sense compared to reducing the design cost.
All foundry/fab numbers are probably best case.
David
