By: --- (---.delete@this.redheron.com), August 5, 2021 4:14 pm
Room: Moderated Discussions
David Kanter (dkanter.delete@this.realworldtech.com) on August 5, 2021 11:08 am wrote:
> Doug S (foo.delete@this.bar.bar) on August 5, 2021 9:19 am wrote:
> > David Kanter (dkanter.delete@this.realworldtech.com) on July 30, 2021 1:52 pm wrote:
> > > So bottom line, FinFETs make dense SRAM a little tricky in addition
> > > to the need for boosting logic to enable good read/write margins.
> >
> >
> > How will the GAAFET / nanosheet transistor type TSMC/Samsung/Intel is transitioning
> > to in the next couple years affect this? Same problem, better, worse...?
>
> That depends. Some GAAFETs, e.g., nanowires, are quantized (K nanowires high, N nanowires
> wide). However, the nanosheets (which I believe Intel is using) are at least somewhat
> variable so it's more like K sheets high, and L nanometers wide. I don't know the extent
> to which L is quantized/discretized. I would assume you cannot freely vary it.
>
> Then there's the question of whether we will have a separate
> process for dense SRAM entirely and just 3D stack it.
>
> Remember that IBM totally abandoned doing dense SRAM because they believed they could just use eDRAM.
>
> David
IF the primary problem is routing density (ie the minimal size of the SRAM cell is now determined by wire, not by transistor size), then what really matters is techniques that alleviate this wire congestion. In other words buried power rail and its immediate successor, buried clock tree.
Let's see who's first out the gate in actually shipping...
Of course once you have that working, you can start to become more ambitious...
https://sites.utexas.edu/CRL/files/2020/12/BBL_SRAM_Rahul_IEDM2020.pdf
> Doug S (foo.delete@this.bar.bar) on August 5, 2021 9:19 am wrote:
> > David Kanter (dkanter.delete@this.realworldtech.com) on July 30, 2021 1:52 pm wrote:
> > > So bottom line, FinFETs make dense SRAM a little tricky in addition
> > > to the need for boosting logic to enable good read/write margins.
> >
> >
> > How will the GAAFET / nanosheet transistor type TSMC/Samsung/Intel is transitioning
> > to in the next couple years affect this? Same problem, better, worse...?
>
> That depends. Some GAAFETs, e.g., nanowires, are quantized (K nanowires high, N nanowires
> wide). However, the nanosheets (which I believe Intel is using) are at least somewhat
> variable so it's more like K sheets high, and L nanometers wide. I don't know the extent
> to which L is quantized/discretized. I would assume you cannot freely vary it.
>
> Then there's the question of whether we will have a separate
> process for dense SRAM entirely and just 3D stack it.
>
> Remember that IBM totally abandoned doing dense SRAM because they believed they could just use eDRAM.
>
> David
IF the primary problem is routing density (ie the minimal size of the SRAM cell is now determined by wire, not by transistor size), then what really matters is techniques that alleviate this wire congestion. In other words buried power rail and its immediate successor, buried clock tree.
Let's see who's first out the gate in actually shipping...
Of course once you have that working, you can start to become more ambitious...
https://sites.utexas.edu/CRL/files/2020/12/BBL_SRAM_Rahul_IEDM2020.pdf
