Post RISC Banked Register Instructions

By: Brett (ggtgp.delete@this.yahoo.com), August 16, 2021 12:38 am
Room: Moderated Discussions
See the Texas Instruments C64 which has two banks enabling wider execution without excessive porting requirements.

Because all the banks are separate with their own rename and porting each bank can run 6 wide giving a huge leap in top performance.

My approach has 5 banks, primary, secondary and three more that are mapped from the old vector register file.
Three or four bits in the instruction pick which collection of banks the instruction applies to; primary, secondary, both, all but primary, etc.

Instructions include which banks and whether a splat is involved, with most cross bank communication being via splats. Many loads will be load pair splats so all addressing can take place in the first two banks.

Add.12 r2,r17,r22 ; first two banks run same instruction.
Add.1s2 r2,r17,r22 ; add bank 1 but also splat result banks 2.
Add.1sA r2,r17,r22 ; add bank 1 but also splat result to all banks.

This instruction set enables easy software unrolling of loops across the banks just using the bank tagging bits in the instructions. Typically the primary bank just doing load/stores and loop count, with the four other banks doing a four way unroll on code that is otherwise resistant to vectorization. 30 wide execution instead of 6.

For backward compatibility with x86 or RISC just add a decoder for that arch.

Thoughts and criticism?
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TopicPosted ByDate
Post RISC Banked Register InstructionsBrett2021/08/16 12:38 AM
  Post RISC Banked Register Instructionsanon2021/08/16 06:37 AM
    Post RISC Banked Register InstructionsBrett2021/08/16 08:46 PM
  Post RISC Banked Register InstructionsHeikki Kultala2021/08/16 07:58 AM
    Post RISC Banked Register InstructionsBrett2021/08/16 01:54 PM
      Still makes no sense at allHeikki Kultala2021/08/17 06:19 AM
        Still makes no sense at allwumpus2021/08/17 09:47 AM
          Still makes no sense at allBrett2021/08/17 02:38 PM
            Still makes no sense at allwumpus2021/08/18 09:46 AM
              Still makes no sense at alldmcq2021/08/18 03:12 PM
                Still makes no sense at allBrett2021/08/18 10:22 PM
                  Still makes no sense at all---2021/08/19 09:48 AM
                    Still makes no sense at allanon2021/08/20 02:58 AM
        Still makes no sense at allBrett2021/08/17 02:33 PM
  The modern problems are storage and interconnect, not CPU design (NT)blaine2021/08/16 01:03 PM
    The modern problems are storage and interconnect, not CPU designwumpus2021/08/17 10:05 AM
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