By: Hugo Décharnes (hdecharn.delete@this.outlook.fr), August 19, 2021 1:33 am
Room: Moderated Discussions
I think the Alpha 21264 scheme sounds rather similar except it wasn't random, it depended on whether the original register number was odd or even.The Alpha 21264 has two clusters, but their register file is not split. They replicate their content, with a 1 cycle delay when the operand is produced by the execution unit of the other cluster.
In the design I described, the two banks content is exclusive. And the core principle is that wake-up latency is homogeneous.
| Topic | Posted By | Date |
|---|---|---|
| Very-large superscalar execution without the cost | Hugo Décharnes | 2021/08/18 10:34 AM |
| Very-large superscalar execution without the cost | dmcq | 2021/08/18 02:56 PM |
| Very-large superscalar execution without the cost | Hugo Décharnes | 2021/08/19 01:33 AM |
| Very-large superscalar execution without the cost | anon | 2021/08/19 08:15 AM |
| Very-large superscalar execution without the cost | Hugo Décharnes | 2021/08/19 08:34 AM |
