By: Adrian (a.delete@this.acm.org), August 19, 2021 5:21 am
Room: Moderated Discussions
From the details released now about Alder Lake, the most significant seems to be that Intel has finally passed from 4 instruction decoders to 6 instruction decoders.
Alder Lake also now matches Zen 3 with 8 instructions fetched per cycle from the uop cache.
This was somewhat expected, because otherwise the increase in IPC announced by Intel would have been very hard to achieve, but now it is confirmed.
https://www.anandtech.com/show/16881/a-deep-dive-into-intels-alder-lake-microarchitectures
| Topic | Posted By | Date |
|---|---|---|
| Alder Lake: 1st Intel/AMD CPU with 6 instruction decoders | Adrian | 2021/08/19 05:21 AM |
| Alder Lake: the Intel presentation | Adrian | 2021/08/19 05:33 AM |
| Intel Mount Evans with 16 ARM Neoverse N1 cores | Adrian | 2021/08/19 05:50 AM |
| No AVX-512? | me | 2021/08/19 06:05 AM |
| No AVX-512? | Adrian | 2021/08/19 06:40 AM |
| No AVX-512? | me | 2021/08/19 06:48 AM |
| No AVX-512? | Adrian | 2021/08/19 07:01 AM |
| No AVX-512? | Michael S | 2021/08/19 07:07 AM |
| No AVX-512? | Adrian | 2021/08/19 07:11 AM |
| No AVX-512? | me | 2021/08/19 07:16 AM |
| No AVX-512? | Adrian | 2021/08/19 07:48 AM |
| No AVX-512? | me | 2021/08/19 10:41 AM |
| No AVX-512? | Adrian | 2021/08/19 11:32 AM |
| No AVX-512? | me | 2021/08/19 12:00 PM |
| No AVX-512? | yangrq | 2021/08/19 12:02 PM |
| No AVX-512? | Adrian | 2021/08/19 12:37 PM |
| No AVX-512? | me | 2021/08/19 02:46 PM |
| No AVX-512? | Adrian | 2021/08/19 09:22 PM |
| No AVX-512? | yangrq | 2021/08/19 10:05 PM |
| No AVX-512? | me | 2021/08/20 03:16 AM |
| No AVX-512? | Robert Williams | 2021/08/20 07:23 AM |
| No AVX-512? | David Hess | 2021/08/20 09:43 AM |
| No AVX-512? | me | 2021/08/20 11:09 AM |
| No AVX-512? | David Hess | 2021/08/20 11:29 AM |
| No AVX-512? | me | 2021/08/20 04:36 PM |
| No AVX-512? | David Hess | 2021/08/26 07:28 PM |
| No AVX-512? | Andrey | 2021/08/27 03:08 AM |
| No AVX-512? | me | 2021/08/27 03:09 PM |
| No AVX-512? | David Hess | 2021/08/28 09:32 AM |
| No AVX-512? | Linus Torvalds | 2021/08/28 11:15 AM |
| Multithreading vs. SIMD | Andrey | 2021/08/28 12:21 PM |
| Multithreading vs. SIMD | rwessel | 2021/08/28 02:44 PM |
| Multithreading vs. SIMD | Linus Torvalds | 2021/08/28 03:18 PM |
| Multithreading vs. SIMD | -.- | 2021/08/28 05:44 PM |
| Multithreading vs. SIMD | Andrey | 2021/08/28 06:31 PM |
| Multithreading vs. SIMD | Adrian | 2021/08/28 08:34 PM |
| Multithreading vs. SIMD | Jukka Larja | 2021/08/29 12:22 AM |
| Multithreading vs. SIMD | Andrey | 2021/08/29 01:10 AM |
| Multithreading vs. SIMD | Michael S | 2021/08/29 01:56 AM |
| Multithreading vs. SIMD | Linus Torvalds | 2021/08/29 09:24 AM |
| Multithreading vs. SIMD | me | 2021/08/29 10:12 AM |
| Multithreading vs. SIMD | Jörn Engel | 2021/08/29 12:50 PM |
| Multithreading vs. SIMD | -.- | 2021/08/29 02:31 PM |
| Multithreading vs. SIMD | Adrian | 2021/08/28 08:18 PM |
| Multithreading vs. SIMD | Michael S | 2021/08/29 01:13 AM |
| Litle cores also give more threads/area | Heikki Kultala | 2021/08/29 12:18 AM |
| No AVX-512? | Adrian | 2021/08/28 08:12 PM |
| No AVX-512? | Doug S | 2021/08/29 06:32 AM |
| No AVX-512? | Adrian | 2021/08/29 10:17 AM |
| No AVX-512? | Romain Dolbeau | 2021/08/29 11:49 PM |
| AVX512, and 256b subsets | David Kanter | 2021/08/22 10:53 AM |
| So just use AVX2? | anonymous2 | 2021/08/20 04:40 PM |
| So just use AVX2? | Laurence Parry | 2021/08/20 05:45 PM |
| So just use AVX2? | Jörn Engel | 2021/08/21 08:24 AM |
| So just use AVX2? | Heikki Kultala | 2021/08/21 12:36 PM |
| So just use AVX2? | Michael S | 2021/08/21 01:58 PM |
| So just use AVX2? | None | 2021/08/22 01:42 AM |
| So just use AVX2? | Michael S | 2021/08/22 02:21 AM |
| So just use AVX2? | None | 2021/08/22 04:31 AM |
| So just use AVX2? | Michael S | 2021/08/22 11:06 AM |
| Intel Mount Evans with 16 ARM Neoverse N1 cores | Michael S | 2021/08/19 06:41 AM |
| Intel Mount Evans with 16 ARM Neoverse N1 cores | Adrian | 2021/08/19 06:49 AM |
| Intel Mount Evans with 16 ARM Neoverse N1 cores | Beastian | 2021/08/19 06:53 AM |
| Gracemont efficiency | Adrian | 2021/08/19 11:07 PM |
| Gracemont efficiency | Foo_ | 2021/08/21 06:46 AM |
| Gracemont efficiency | rwessel | 2021/08/21 08:56 AM |
| Gracemont efficiency | Foo_ | 2021/08/21 09:07 AM |
| Gracemont efficiency | David Hess | 2021/08/27 01:16 AM |
| Gracemont efficiency | --- | 2021/08/21 08:57 AM |
| Gracemont efficiency | David Hess | 2021/08/27 01:25 AM |
| Gracemont efficiency | Adrian | 2021/08/21 09:33 AM |
| Gracemont efficiency | Groo | 2021/08/21 10:39 AM |
| Gracemont efficiency | me | 2021/08/21 11:13 AM |
| Gracemont efficiency | Michael S | 2021/08/21 11:49 AM |
| Gracemont efficiency | me | 2021/08/21 12:12 PM |
| Gracemont efficiency | Groo | 2021/08/21 02:29 PM |
| Gracemont efficiency | Adrian | 2021/08/21 12:08 PM |
| Gracemont efficiency | sylt | 2021/08/22 12:25 AM |
| Gracemont efficiency | Adrian | 2021/08/22 03:18 AM |
| Gracemont efficiency | rwessel | 2021/08/22 06:31 AM |
| Gracemont efficiency | Jukka Larja | 2021/08/22 07:45 AM |
| Gracemont efficiency | Gabriele Svelto | 2021/08/23 08:44 AM |
| Gracemont efficiency | gallier2 | 2021/08/24 06:29 AM |
| Gracemont efficiency | Gabriele Svelto | 2021/08/24 11:40 PM |
| Gracemont efficiency | gallier2 | 2021/08/25 12:40 PM |
| Gracemont efficiency | Gabriele Svelto | 2021/08/23 12:47 AM |
| Gracemont efficiency | sylt | 2021/08/23 12:26 PM |
| Gracemont efficiency | --- | 2021/08/23 01:19 PM |
| Gracemont efficiency | Doug S | 2021/08/22 06:45 AM |
| Gracemont efficiency | Jukka Larja | 2021/08/22 07:44 AM |
| Gracemont efficiency | Adrian | 2021/08/22 08:33 AM |
| Gracemont efficiency | Adrian | 2021/08/21 11:47 AM |
| Alder Lake: 1st Intel/AMD CPU with 6 instruction decoders | Linus Torvalds | 2021/08/19 04:36 PM |
| Alder Lake: 1st Intel/AMD CPU with 6 instruction decoders | Adrian | 2021/08/19 09:29 PM |
| Alder Lake: 1st Intel/AMD CPU with 6 instruction decoders | Mark Roulo | 2021/08/20 09:19 AM |
| Alder Lake: 1st Intel/AMD CPU with 6 instruction decoders | Linus Torvalds | 2021/08/20 10:12 AM |
| Alder Lake: 1st Intel/AMD CPU with 6 instruction decoders | Adrian | 2021/08/20 12:00 PM |
| Alder Lake: 1st Intel/AMD CPU with 6 instruction decoders | Linus Torvalds | 2021/08/20 12:38 PM |
| 32B pre-decode probably more important | David Kanter | 2021/08/21 07:56 PM |
| 32B pre-decode probably more important | Adrian | 2021/08/22 03:52 AM |
| 32B pre-decode probably more important | Mark Roulo | 2021/08/22 08:06 AM |
| 32B pre-decode probably more important | Linus Torvalds | 2021/08/22 10:07 AM |
| 32B pre-decode probably more important | Doug S | 2021/08/22 01:20 PM |
| 32B pre-decode probably more important | me | 2021/08/22 05:34 PM |
| 32B pre-decode probably more important | Jukka Larja | 2021/08/23 05:46 AM |
| 32B pre-decode probably more important | me | 2021/08/23 04:33 PM |
| 32B pre-decode probably more important | Jukka Larja | 2021/08/24 05:47 AM |
| 32B pre-decode probably more important | Mark Roulo | 2021/08/23 06:48 AM |
| 32B pre-decode probably more important | Matt Sayler | 2021/08/23 09:59 AM |
| 32B pre-decode probably more important | Doug S | 2021/08/23 10:14 AM |
| 32B pre-decode probably more important | Carson | 2021/08/24 10:45 PM |
| 32B pre-decode probably more important | Doug S | 2021/08/25 10:32 AM |
| 32B pre-decode probably more important | Carson | 2021/08/25 10:31 PM |
| 32B pre-decode probably more important | Jukka Larja | 2021/08/26 04:39 AM |
| 32B pre-decode probably more important | Adrian | 2021/08/26 04:54 AM |
| 32B pre-decode probably more important | Carson | 2021/08/27 02:26 AM |
| 32B pre-decode probably more important | Doug S | 2021/08/26 10:34 AM |
| 32B pre-decode probably more important | Carson | 2021/08/27 02:22 AM |
| 32B pre-decode probably more important | Andrey | 2021/08/27 05:25 AM |
| 32B pre-decode probably more important | Doug S | 2021/08/27 09:08 AM |
| 32B pre-decode probably more important | Adrian | 2021/08/27 09:42 AM |
| Intel 22 nm - 10 nm | Mark Roulo | 2021/08/27 09:47 AM |
| Intel 22 nm - 10 nm | me | 2021/08/27 10:43 AM |
| Intel 22 nm - 10 nm | Andrey | 2021/08/27 11:03 AM |
| Intel 22 nm - 10 nm | Groo | 2021/08/27 08:02 PM |
| 32B pre-decode probably more important | David Hess | 2021/08/28 10:45 AM |
| 32B pre-decode probably more important | David Kanter | 2021/08/25 12:57 PM |
| 32B pre-decode probably more important | --- | 2021/08/25 03:12 PM |
| 32B pre-decode probably more important | Doug S | 2021/08/25 07:45 PM |
| Cloud pricing | Anon | 2021/08/27 08:59 AM |
| Cloud pricing | Doug S | 2021/08/27 09:17 AM |
| Apples low-end | Heikki Kultala | 2021/08/25 03:02 AM |
| Apples low-end | Jukka Larja | 2021/08/25 08:11 AM |
| Apples low-end | --- | 2021/08/25 08:30 AM |
| Apples low-end | Doug S | 2021/08/25 10:22 AM |
| Apples low-end | Maxwell | 2021/08/25 10:56 PM |
| Apples low-end | Jose | 2021/08/26 04:18 AM |
| Apples low-end | Jukka Larja | 2021/08/26 04:34 AM |
| Apples low-end | --- | 2021/08/26 08:43 AM |
| Apples low-end | Jukka Larja | 2021/08/27 02:41 AM |
| Apples low-end | Doug S | 2021/08/25 10:29 AM |