Was Intel Holding Back?

By: Adrian (a.delete@this.acm.org), August 19, 2021 8:34 am
Room: Moderated Discussions
Jon (no.delete@this.no.com) on August 19, 2021 7:49 am wrote:
> I just noticed that Intel had its arch day today.
> I remember that for years when Broadwell was introduced we had lengthy arguments over that theoretical
> x86 IPC wall. Some attributed Intel's lackluster IPC improvements to a theoretical IPC wall of
> the x86 ISA. Others simply argued that Intel was holding back due to lack of sufficient competition.
> Now that know Golden Cove does another 1.2x IPC, it brings the number to 1.45x IPC improvement
> over Skylake in single thread integer workload. Given that's more/about what Intel did from Sandy
> Bridge to Skylake, it sure feels like they were simply holding back?
> details of Golden Cove:
> https://www.anandtech.com/show/16881/a-deep-dive-into-intels-alder-lake-microarchitectures/3
> https://fuse.wikichip.org/news/6111/intel-details-golden-cove-next-generation-big-core-for-client-and-server-socs/

Intel has been stuck for many, many years at decoding up to 4 instructions from up to 16 bytes.

Most improvements in IPC during the 10 years from Sandy Bridge until now worked only for the loops or procedures that can be fetched from the uop cache, otherwise fetching and decoding was the bottleneck.

Now Alder Lake can decode up to 6 instructions from up to 32 bytes.
This is certain to cause a very large IPC increase for anything that cannot be found in the uop cache.

The uop cache throughput has also been increased enough.

There is no doubt that the last time when there was such a large improvement in the front-end was in Sandy Bridge, with the introduction of the uop cache.

About holding back, this has been an Intel policy since forever.

Making the best CPU that you can increases the production cost.
The greatest profit is obtained when each product generation has as few improvements as the customers will accept, because the production costs are lower, while the selling price is the same.

As long as the competition was weak, Intel has always delayed as much as possible any improvements. They could have easily included FMA in Sandy Bridge, but they waited until Haswell to introduce it. They could have introduced the Larrabee New Instructions (now known as AVX-512) in Sandy Bridge, instead of the crippled AVX instruction set (I am referring to the Larrabee operations, with mask registers & scatter/gather, not to the 512-bit width which would not have been worthwhile yet).

There are a huge number of such examples. I accept that this is the rational choice for any company that wants profit, but nonetheless I hate this Intel policy.

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TopicPosted ByDate
Was Intel Holding Back?Jon2021/08/19 07:49 AM
  Was Intel Holding Back?Adrian2021/08/19 08:34 AM
  Was Intel Holding Back?dmcq2021/08/19 11:36 AM
    Was Intel Holding Back?me2021/08/19 12:03 PM
      Was Intel Holding Back?Groo2021/08/19 04:46 PM
  Was Intel Holding Back?2021/08/19 11:37 AM
  Was Intel Holding Back?James2021/08/19 03:52 PM
  Was Intel Holding Back?juanrga2021/08/20 01:53 AM
    Was Intel Holding Back?2021/08/20 09:52 AM
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