Was Intel Holding Back?

By: (0xe2.0x9a.0x9b.delete@this.gmail.com), August 19, 2021 11:37 am
Room: Moderated Discussions
Jon (no.delete@this.no.com) on August 19, 2021 7:49 am wrote:
> I just noticed that Intel had its arch day today.
> I remember that for years when Broadwell was introduced we had lengthy arguments over that theoretical
> x86 IPC wall. Some attributed Intel's lackluster IPC improvements to a theoretical IPC wall of
> the x86 ISA. Others simply argued that Intel was holding back due to lack of sufficient competition.
> Now that know Golden Cove does another 1.2x IPC, it brings the number to 1.45x IPC improvement
> over Skylake in single thread integer workload. Given that's more/about what Intel did from Sandy
> Bridge to Skylake, it sure feels like they were simply holding back?
> details of Golden Cove:
> https://www.anandtech.com/show/16881/a-deep-dive-into-intels-alder-lake-microarchitectures/3
> https://fuse.wikichip.org/news/6111/intel-details-golden-cove-next-generation-big-core-for-client-and-server-socs/

In the case of "normal" applications written in "normal" programming languages such as C/Go/Rust/etc, the theoretical IPC wall of x86 ISA (preprocessed in a µop cache) is definitely beyond 10 x86 instructions per clock.

A "normal" application is an application that is spending at least 50% of execution time in various loops *and* that uses sequential operational semantics and sequential data formats to encode otherwise naturally concurrent concepts - which covers a sizeable portion of real-world applications.

A single high-performance CPU *core* executing code of a highly-concurrent general-purpose programming language (which - for example - does *not* include the Go programming language) is currently unable to outperform a sequential programming style because the performance of the concurrent one is severely limited by memory bandwidth (and also by the absence of helper instructions in the x86 ISA). With x86 CPU cores slowly evolving into being able to process multiple loads&stores per cycle, it is probable that programming languages of the former type will someday overtake the latter type of programming languages. A tipping point is when the number of identical replicas of an integer ALU in a single CPU core exceeds the number of programmer-visible x86 registers.

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TopicPosted ByDate
Was Intel Holding Back?Jon2021/08/19 07:49 AM
  Was Intel Holding Back?Adrian2021/08/19 08:34 AM
  Was Intel Holding Back?dmcq2021/08/19 11:36 AM
    Was Intel Holding Back?me2021/08/19 12:03 PM
      Was Intel Holding Back?Groo2021/08/19 04:46 PM
  Was Intel Holding Back?2021/08/19 11:37 AM
  Was Intel Holding Back?James2021/08/19 03:52 PM
  Was Intel Holding Back?juanrga2021/08/20 01:53 AM
    Was Intel Holding Back?2021/08/20 09:52 AM
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