By: ⚛ (0xe2.0x9a.0x9b.delete@this.gmail.com), August 20, 2021 9:52 am
Room: Moderated Discussions
juanrga (nomail.delete@this.juanrga.com) on August 20, 2021 1:53 am wrote:
> Jon (no.delete@this.no.com) on August 19, 2021 7:49 am wrote:
> > I just noticed that Intel had its arch day today.
> >
> >
> > I remember that for years when Broadwell was introduced we had lengthy arguments over that theoretical
> > x86 IPC wall.
>
> It isn't just theoretical, it is measurable. Just plot IPC
> vs year since the first x86 chips and see for yourself.
How does the x86-IPC-wall theory account for increases in the number (2 and more) of branches predicted per cycle?
On x86/etc, which doesn't have an addressable register file (e.g: ADDQ (REGFILE,%rax), %rbx), branches per cycle has a correlation with the number of loads&stores per cycle.
-atom
> Jon (no.delete@this.no.com) on August 19, 2021 7:49 am wrote:
> > I just noticed that Intel had its arch day today.
> >
> >
> > I remember that for years when Broadwell was introduced we had lengthy arguments over that theoretical
> > x86 IPC wall.
>
> It isn't just theoretical, it is measurable. Just plot IPC
> vs year since the first x86 chips and see for yourself.
How does the x86-IPC-wall theory account for increases in the number (2 and more) of branches predicted per cycle?
On x86/etc, which doesn't have an addressable register file (e.g: ADDQ (REGFILE,%rax), %rbx), branches per cycle has a correlation with the number of loads&stores per cycle.
-atom
Topic | Posted By | Date |
---|---|---|
Was Intel Holding Back? | Jon | 2021/08/19 07:49 AM |
Was Intel Holding Back? | Adrian | 2021/08/19 08:34 AM |
Was Intel Holding Back? | dmcq | 2021/08/19 11:36 AM |
Was Intel Holding Back? | me | 2021/08/19 12:03 PM |
Was Intel Holding Back? | Groo | 2021/08/19 04:46 PM |
Was Intel Holding Back? | ⚛ | 2021/08/19 11:37 AM |
Was Intel Holding Back? | James | 2021/08/19 03:52 PM |
Was Intel Holding Back? | juanrga | 2021/08/20 01:53 AM |
Was Intel Holding Back? | ⚛ | 2021/08/20 09:52 AM |