By: Michael S (already5chosen.delete@this.yahoo.com), August 24, 2021 2:43 am
Room: Moderated Discussions
- every core has access
- new instructions for AI accelerator
- but you have to use the libraries to use the instructions
All three aspects appear the same as Apple's:
1== Not coupled to particular core, but exposed to [system] SW as if coupled.
2== Accessed through ISA extension rather than memory-mapped I/O or moves into/out of SPRs
3== But IBM prefers to not make an extension public, probably to avoid obligations of compatibility in future generations
I wonder if IBM tried the strategy of non-public ISA extensions in S/360 derivatives in the past.
- new instructions for AI accelerator
- but you have to use the libraries to use the instructions
All three aspects appear the same as Apple's:
1== Not coupled to particular core, but exposed to [system] SW as if coupled.
2== Accessed through ISA extension rather than memory-mapped I/O or moves into/out of SPRs
3== But IBM prefers to not make an extension public, probably to avoid obligations of compatibility in future generations
I wonder if IBM tried the strategy of non-public ISA extensions in S/360 derivatives in the past.
| Topic | Posted By | Date |
|---|---|---|
| IBM's AMX - Apple's way | Michael S | 2021/08/24 02:43 AM |
| IBM's AMX - Apple's way | rwessel | 2021/08/24 05:10 AM |
| IBM's AMX - Apple's way | Mark Roulo | 2021/08/24 08:07 AM |
| IBM's AMX - Apple's way | zArchJon | 2021/08/24 10:19 AM |
| IBM's AMX - Apple's way | Michael S | 2021/08/24 10:26 AM |
| IBM's AMX - Apple's way | zArchJon | 2021/08/24 10:41 AM |
| IBM's AMX - Apple's way | Michael S | 2021/08/24 10:52 AM |
| IBM's AMX - Apple's way | rwessel | 2021/08/25 06:04 AM |
