By: -.- (blarg.delete@this.mailinator.com), August 29, 2021 4:05 am
Room: Moderated Discussions
ARM's upcoming Cortex A510 uses a shared FPU between two cores, so there's at least a second mainstream player trying out shared FPUs:
I recall Bulldozer had minimum 2 cycle latency FPU ops, and current ARM chips generally also have minimum 2 cycle latency FPU ops.
I recall Bulldozer had minimum 2 cycle latency FPU ops, and current ARM chips generally also have minimum 2 cycle latency FPU ops.
