Hugo Décharnes (hdecharn.delete@this.outlook.fr) on September 8, 2021 8:58 am wrote:
> Issue is, if the virtual tag comparison is on the path of the translation, then your L2 access
> time is increased (assuming L2 is PIPT). Also, there is the need for scrubbing the cache upon
> TLBI, if no physical tag confirmation is done, to make those targeted lines unhitable by load/store
> (though still evictable and snoopable). From a performance and power perspective, it is better
> to have a partial virtual tag, and a full physical one, used later for confirmation.


L2 access time is compensated as TLB translation could use magnitude of order more power per translation, so it can be made faster and more accurate.

And nobody does pure virtual L1 cache anymore, those cache lines are double tagged, they got both virtual and physical tags so cache can be accessed without address translation from core side, and cache can be accessed from other cores by physical tag. And no cache flush is needed when scrubbing virtual tags as physical tags remain.

Double tagging was very well known already at 80's but wasn't used because silicon space was better utilized to something else and instead power was used to translate addresses for every memory access, but that has probably changed to double tagging already ten or twenty years ago.