Point for VIVT L1 is that there's zero need to burn power for TLB translation for L1 hit. Data already in cache can accessed and verified without need to translate address. As CPU core can do many L1-operations per cycle at least for L1-data TLB needs to be multiported, where instead L2 can service only one request per clock so single-ported TLB will be fine.

This requires a full VA tagging, plus ASID and VMID comparison (there is not one VA space). Absence of PA tag check implies scrubbing the cache on TLBI, which, as explained earlier, is undesirable.

Think about it, how energy-efficient would 64 way fully associative triple ported every cycle accessible TLB be? If someone has such a structure in their design getting rid of it would increase power-efficiency of design massively.....

Well, I think about it. I’m a design engineer.
With a VIVPT cache, you do not need such high associativity. The primary reason for fully associative 1st-level TLB (aka. micro-TLB or L1-TLB, depending on design) is that the VA is directly driven to a CAM structure, which yields, from experience, to better timings than what would have been with a set-associative structure with the same number of entries. (This statement is true in a limited range, though.) Thus, one can benefit from the fact the 1st-level TLB is not on the critical path (way-select) to make it bigger and gently set-associative, and why not in SRAM. That will save power.
But at the end of the day, the power drawn by the 1st-level TLB is peanuts. Issue queues, vector units, and L2 burn so much power compared to it. Yes, every bit matters, but frankly, it’d be better to optimize those structures first.