Hugo Décharnes (hdecharn.delete@this.outlook.fr) on September 8, 2021 12:23 pm wrote:
> This requires a full VA tagging, plus ASID and VMID comparison (there is not one VA space). Absence
> of PA tag check implies scrubbing the cache on TLBI, which, as explained earlier, is undesirable.

Full VA taggind is required but it can split for access and verify. L1 can be used as one VA-space, invalidate virtual tags at context switches.

And as I tried to explain, I newer, ever will propose any system where all cachelines would not have full physical tags associated to them. Pure virtual caches aren't practical to about anything, but nothing prevents tagging every cache line with both virtual and physical tags. And physical tags for every cache line exist in every modern system already, either with inclusive caches or shadow tags for inner cache levels. Virtual tags only provide way to use those cache lines without need to address translation.



>Well, I think about it. I’m a design engineer.
> With a VIVPT cache, you do not need such high associativity. The primary reason for fully associative
> 1st-level TLB (aka. micro-TLB or L1-TLB, depending on design) is that the VA is directly driven to
> a CAM structure, which yields, from experience, to better timings than what would have been with a
> set-associative structure with the same number of entries. (This statement is true in a limited range,
> though.) Thus, one can benefit from the fact the 1st-level TLB is not on the critical path (way-select)
> to make it bigger and gently set-associative, and why not in SRAM. That will save power.
> But at the end of the day, the power drawn by the 1st-level TLB is peanuts. Issue
> queues, vector units, and L2 burn so much power compared to it. Yes, every bit
> matters, but frankly, it’d be better to optimize those structures first.


Cam arrays are simple and fast, but with many way associativity and many ports their transistor chains became long.

For that power10 IBM have done very fast TLB for use after L1-miss - is it just a change that it's same 64 way fully associative setup as AMD described to use? AMD does however need to make it triple ported if it's used for every cache access instead of L1-misses.


I do agree that if TLB is made for every cache access it should not be fully associative.


And there was also that link for that IBM Z-mainframe CPU document where it was described that many way associative many ported TLB will easily become the hottest part of a cpu and eventually limit its performance possibilities.