anonymou5 (no.delete@this.spam.com) on September 8, 2021 8:28 pm wrote:
> > The claim that a highly performant TLB must be multi-ported is a myth.
> > The theory is explained here: https://eprints.soton.ac.uk/347147/1/__userfiles.soton.ac.uk_Users_spd
> > _mydesktop _MALEC.pdf
>
> broken link?
>
> > The essential insight is that
> > - most memory requests are strongly clustered to a single page or a few pages
> > - to the extent that requests are spread over many pages, that same code
> > is probably not exactly latency essential to the single cycle level
>
> doesn't sound like modern real world workloads to me, tbh

The link

https://eprints.soton.ac.uk/347147/1/__userfiles.soton.ac.uk_Users_spd_mydesktop_MALEC.pdf

works for me.

Here's an alternative version, or you can search for the title:
MALEC: A Multiple Access Low Energy Cache

(The paper gives *some ideas* that are used by the M1. It is not a description of the M1's cache, which also uses other very different ideas.)

As for your claims about "modern workloads", well, what can I say?
The M1 works this way. And it works very well for Apple's workloads.
You want to deny these two facts, go ahead; I care about explaining, not converting.