--- (---.delete@this.redheron.com) on September 8, 2021 2:28 pm wrote:

> The claim that a highly performant TLB must be multi-ported is a myth.
> The theory is explained here: https://eprints.soton.ac.uk/347147/1/__userfiles.soton.ac.uk_Users_spd
> _mydesktop _MALEC.pdf
>
> The essential insight is that
> - most memory requests are strongly clustered to a single page or a few pages
> - to the extent that requests are spread over many pages, that same code
> is probably not exactly latency essential to the single cycle level


Many people still believes that L1-caches are VIPT. And if you support VIPT with single-ported TLB there will be performance penalties, VIPT is designed to support TLB result simultaneously with physical tag read to allow physical tag comparison. Doing VIPT wiht single-ported TLB would result increased cache latencies when accessed are split to different pages - and consequence is reduced bandwith too. I'm pretty sure that no high performance cpu design will suffers from that kind of performance problems.

And if you want to increase your CPU's performance per watt you should not do unnecessarily work. Doing address conversion for L1 hit validation isn't sane thing to do if it can be avoided. And it can.