--- (---.delete@this.redheron.com) on September 8, 2021 2:28 pm wrote:

> Finally I cannot figure out how Apple bypasses D- way prediction, but they don't seem to need
> it -- at least even the most random stream of addresses (in terms of hitting different ways)
> that I could generate never seemed to cause even a hiccup in terms of invalid way prediction.
> I have a few hypotheses, but no strong leads, and no patents suggest an explanation.
> On the I- side it's easier -- way info is stored in various appropriate places,
> like, for example, the Next Fetch Predictor -- and this is described in patents.

That' way L1-cache tags need to be in program address space. With physical tags it's impossible to do any kind of way prediction with tag bits but with linear address space you could use tag bits itself to do "way prediction". AMD is documented how they do it. It's a "way prediction" because it isn't traditional way prediction where first is compared predicted way and then rest - what they do is to make tags so short that they can compare all ways effectively. So way prediction newer missed, it's either L1 hit or miss.