Hugo Décharnes (hdecharn.delete@this.outlook.fr) on September 8, 2021 10:46 am wrote:
> BTW, L2 access time is critical, and TLB coverage (not accuracy) does not compensate, in that most
> workload are bounded by the cache latency, not the TLB coverage. Yes, VIVPT enables to move TLB away
> from the time-critical load-return path, enabling bigger TLBs. But you must reduce the L2 hit latency
> as much as possible. We are talking about percents of performance for a typical big core.

But you got that if TLB is done late like in VIVPT there's no TLB result available when L1 miss is detected?

And from IBM slides we could guess that power10 has VIPT-L2 cache with hashed linear-address space microtags. So they can start accessing L2 and doing TLB-conversion same time, and because L2 access takes ages they can pipeline TLB to very long. (for 2MB L2 having double tagging would make L2 area like 10% bigger which isn't insignificant anymore)

What I meant about TLB accuracy that for given size they can use better hit-rate schemes if they have enough power budged or time to pipeline TLB access. So in case of 64 slot TLB they could use pipelined fully associative solution instead of 4-way associative with recent use way prediction - basically direct mapped TLB like Intel have been using in some it's older models.


For IBM z-mainframe CPU they documented that they use pipelined TLB for L2 and beyond. Pipelining TLB access makes fully associative scheme possible, instead of doing 64 36(for x86-64) bit comparisons in one clock cycle they can compare few bits or even one bit a time and remove missed ways from next comparison cycle. It even might be the most power efficient way to do L1 TLB, decreasing associativity might reduce hit rate so much that it decrease overall TLB efficiency vs doing it fully associativite.