sr (nobody.delete@this.nowhere.com) on September 12, 2021 12:57 am wrote:
> dmcq (dmcq.delete@this.fano.co.uk) on September 11, 2021 8:59 am wrote:
>
> > Aliasing is a problem, especially with process ids. The same
> > physical address may be mapped to different addresses
> > in different processes. It is very desirable to not do any
> > special work going from one process to another except
> > o prefix the process id to the virtual address. L1 does not
> > really need physical addresses with what I was talking
> > about though at least an index from L1 into L2 and a backward
> > one from L2 to L1 are desirable and there wouldn't
> > be any aliasing in L1 because any previous alias will be evicted or moved to the new slot.
>
> If system has memory coherence, as any sane multithreaded system
> does there have to be system to prevent aliasing in caches.
>
> Modern systems use MESI-coherence with store on exclusive approach - so hardware invalidates
> all other cache instances of shared data before it can give asking cpu core permission to
> modify data. To be able to have such a protocol every line of memory in caches need to have
> full physical tag associated to them and visible to coherence system all the time.
>
> And memory coherence is critical, it won't cure multithreading problems but it makes possible to do working
> locking system to multithreaded code. There have been some less strict coherence requirements like after
> some time memory is in coherence state - so good luck writing working good performance locking algorithm
> for that where your perfectly set and test locking code still might fail after some not specified time.
>
> Today I believe everybody does memory coherence with that store on exclusive state way so there's absolutely
> no way to do cache systems other way than have full physical tag for every cache line system has.

What I was talking about is a VIVT system which does not require any TLB access if data is in L1. You need the TLB flags of course and using an inclusive L2 system make it all easier. You'd have extra loads of L1 for shared data when going between processes, but the cache can be designed without needing to take any account of page sizes so aliasing within a process is reduced. There is no problem about memory coherence because there is only one copy of data in L1. I hope we're not talking too much at cross purposes. MESI is more the concern of L2 here.