sr (nobody.delete@this.nowhere.com) on September 12, 2021 12:43 am wrote:
> so far it seems that TLB trashing for moderns CPU's like Zen and Apple devices start right
> after L1, so L1 doesn't suffer TLB limitation -> L1 is purely virtually accessed.

Note that I think you'd probably still want physical tags in addition to the virtual ones.

The tags don't need to be very big - you just want to be able to find the physically indexed L2 entry from a virtually indexed L1 entry. And assuming your L2 is inclusive of the L1 (which seems a pretty reasonable assumption), that means that you only need enough bits to find that existing L2 entry so that you can do writeback to the right L2 entry.

And since virtual and physical address will still match in the low bits, you really don't need that many tag bits in the L1 to determine the associated L2 entry.

Yeah, yeah, the L2 needs to have the reverse pointer to any inclusive virtually indexed L1 entry. You want that for alias avoidance at L1 fill time, and so that you can flush and/or invalidate the L1 on cache coherency events.

I guess you could drive all L1 writeback from the L2 side (ie L1 never starts writeback on its own, and wouldn't need to find the L2 entry for it). But even outside of writeback, I think having the bits would make L1 replacement a lot easier, though (ie the case where "I want to replace a L1 cache entry, but I need to find the old L2 entry to write back the preexisting L1 data first" - and at replacement time, you have the address of the new data and can look up the new L2 contents that way, but need to find the previous L2 entry for writeback).

Regardless, you wouldn't need to access those tags at L1 access time - they'd be updated and used only for cache flush and replacement.

Linus