sr (nobody.delete@this.nowhere.com) on September 12, 2021 9:48 am wrote:
> dmcq (dmcq.delete@this.fano.co.uk) on September 12, 2021 8:44 am wrote:
>
> > What I was talking about is a VIVT system which does not require any TLB access if data is in
> > L1. You need the TLB flags of course and using an inclusive L2 system make it all easier. You'd
> > have extra loads of L1 for shared data when going between processes, but the cache can be designed
> > without needing to take any account of page sizes so aliasing within a process is reduced. There
> > is no problem about memory coherence because there is only one copy of data in L1. I hope we're
> > not talking too much at cross purposes. MESI is more the concern of L2 here.
>
>
> Data in L1 cache can be accessed VIVT from core if it has virtual tags.
> But every cache line also needs physical tags for coherence system.
>
>
> If you have system being able to do only single-threading per process you only need to take
> care of aliasing lines between different address spaces. But as today every system is also being
> able to do simultaneous multithreading in same address space that same virtual address and its
> data could been shared between many cores, so that data can exist in many L1 caches.
>
>
> SMP-system with memory coherence with strict store-allocate (store is permitted only to exclusive
> state cache line) guarantees that every byte read from memory is in every clock cycle in coherent
> state. If your core A writes byte Y to address X in the same or next clock cycle any other core
> reading from address X from memory will get that byte Y as result.( it does not guarantee that
> cpus are in coherent state - data can be read from CPU buffers instead of cache and be out of sync
> - but properly done code flushing cpu buffers(atomic instructions should do) and so on can be made
> bug-free.) It also prevents two cores from writing to same cache line at same time.
>
> That memory coherence is strict requirement for any sane SMP-system. x86 and less
> strict memory ordering rule systems all use it. TSO instead isn't bringing any real
> effect on coherence, it only can make bugs from buggy code to be less frequent.
>
> And being able to make that memory coherence every cache line in system needs all time visible
> full address space physical tags. That makes possible that all memory mapped in system can
> be controlled via one address space instead of programs many virtual address spaces.

I'm afraid I'm finding it hard to follow you. SMT would give some problems with what I was talking about but not SMP. With an inclusive L2 one only needs an index into L2 not a full physical address, the L2 could hold the full address, that isn't much of a problem one way or the other though. You seem to be trying to explain memory coherence to me, what is it I said that makes you think I am misunderstanding something about it?