Michael S (already5chosen.delete@this.yahoo.com) on September 16, 2021 10:13 am wrote:
> Konrad Schwarz (no.spam.delete@this.no.spam) on September 16, 2021 4:24 am wrote:
> > dmcq (dmcq.delete@this.fano.co.uk) on September 15, 2021 3:42 pm wrote:
> > > Michael S (already5chosen.delete@this.yahoo.com) on September 15, 2021 3:21 am wrote:
> > > > I don't think that PLBs exist on any of today's general-purpose computers.
> > > > Paul A. Clayton probably picked the idea from Ivan Godard's Mill.
> > > >
> > > > http://millcomputing.com/wiki/Protection
> > >
> > > Isn't it the sort of thing used in lots of microcontrollers?
> >
> > Looks like it;
>
> Looks like it is not.
>
> > ARM terminology is Memory Protection Unit (MPU),
> > used in -R and -M class cores, in contrast to the MMU used
> > in -A class cores.
> >
> > A difference to the PLB may be that the MPU is static and has a fixed
> > number of (variably-sized) regions; no caching is involved.
>
> Exactly. Not similar at all.


PowerPC had BAT registers (4I+4D registers that defined a variable sized region of memory with particular properties).
You might think that's obsolete (or, the equivalent, basically embedded these days) -- as far as I know POWER does not use BATs. BUT (and you all know where this is going...)
Apple appear to be using range registers (ie BATs) in their cores. At least there are patents
to this effect, eg https://patents.google.com/patent/US8392658B2 (look at Fig 4).

(The rest of the patent is also interesting; the idea is to be able to record in a cache tag whether that block should be subject to LRU replacement [normal] or MRU replacement [streaming].
Of course there are multiple ways to get at parts of this, eg NonTemporal prefetch instructions; but the Apple scheme seems to have in mind augmenting these by being able to indicate, in the page table or a range register, that this block of memory is best handled as streaming rather than LRU, and having that just propagate through the system so that, even while using standard load/stores, streaming-tagged cache blocks will automatically do the right thing as soon as replacement is required.)

Perhaps once the Asahi folks have figured out the basics they are working on, they will have more to say about this?

Of course the "primary" address mapping and protection on Apple cores (like PPC) is via page tables; but BATs or range registers are available as a useful extension to handle various common and otherwise problematic cases. Display RAM is an obvious immediate example, but I suspect that once you have the tech, an OS can figure out a number of ways to use it for quick and dirty situations where modifying the page tables is more heavyweight than really required. (Similar, in that way, to the permissions indirection of SPPR https://patents.google.com/patent/US20210064539A1 )