Michael S (already5chosen.delete@this.yahoo.com) on September 18, 2021 4:14 pm wrote:
[snip]
> With permission coarser-grained than translation how are you going to emulate a Present bit in PTE?
> Or do you propose to totally give up on demand paging?

One would probably place present/valid, accessed, and dirty bits along with the translation (though, if one was willing to consider global activity and use specialized hardware, one could associate accessed and dirty with the physical memory location — having "hardware" aware of such state might be useful). (If one has an invalid page address, one could use that to indicate not-present, but such is usually not considered a worthwhile compression.)

(This would mean that the processor would be made aware of a 'memory miss' later than with a traditional system. If such was sufficiently important, one could effectively prefetch and cache present/valid information.)

There are doubtless other techniques that could be used, but the above is the obvious minimum difference mechanism.

(I disagree with the TLB location proposed for the Mill — after the last-level cache — as such ignores the advantages of "memory-side" caches, but that is a microarchitectural detail.)