dmcq (dmcq.delete@this.fano.co.uk) on September 13, 2021 8:31 am wrote:
> What you are talking about is straightforward and simple but not necessary. There is no absolute
> requirement that all possible fillings of L1 be mirrored in L2. If it isn't possible then the basic
> requirement of inclusion can be met by having some bits of L1 not filled because it would require
> too great a clash in L2. And it may be that L1 can be better filled with useful stuff by avoiding
> clashes in the low end parts of addresses. As they say, there's more than one way to skin a cat.

What they want to do is to get rid of L1 write-backs. As simple as they are for low FO4-design many associative writeback-scheme for L1 is too costly to implement. It will lower L1-hit rate, reduce L2-L1 bandwidth and so on.

So if designer doesn't know inclusive cache system well he might opt to go for write-through L1. Free and fast replacement policy for L1 and coalescing buffer for bending L2 writes to wait idle L2 cycles instead of writebacks robbing L2 read bandwidth.

But if inclusive cache system is well known designer might opt to get rid of writebacks in different way. By mapping L1 as subset of L2. For 64 byte cachelines and 4KB pages there is six bit that do not change at address translation so addresses can be interleaved up to 64 ways. If done with 8-way set 32KB L1 there's 64 cache lines in 4KB L1-slice, which are hardware set to eight sets. If L2 is 256KB also eight way interleaved there is 512 cache lines per slice, which can interleaved with those 6 bits not changing with address translation to 64 slices that map directly to every L1 set. That 64 line slice can then be indexed to 8 sets of 8 where one of lines are always mapped to L1. And point of doing so is that when compatible set is open for both L1 and L2 swapping lines between those caches becomes basically free.

Intel did go even further, they did do 3-way inclusive cache system where L1-victims could go directly back to L3, may be whole write-back policy was controlled from L3. But as there is some sidechannels with inclusive caches going inclusive all the way to shared cache between cores might be a bad idea for security they step back to 2-way system with Willow Cove.