dmcq (dmcq.delete@this.fano.co.uk) on September 12, 2021 1:22 pm wrote:

> I'm afraid I'm finding it hard to follow you. SMT would give some problems with what I was talking about but
> not SMP. With an inclusive L2 one only needs an index into L2 not a full physical address, the L2 could hold
> the full address, that isn't much of a problem one way or the other though. You seem to be trying to explain
> memory coherence to me, what is it I said that makes you think I am misunderstanding something about it?

Yeah, sorry about that.


But what I argued against is that you said MESI-isn't needed for L1. It is, memory coherence protocol needs it in any SMP-system that has memory coherence.


Any cpu in coherence memory system can write only to exclusive-state cache lines. Exclusive state is given to any cache line that it's not shared but in multi-threading cabable SMP systems it's perfectly legal to share memory between cores. And if same address space memory is shared between different cores cache system has aliases in same virtual address space. SMP system needs to resolve those too. And those are resolved by that same physical-address tagged coherence system that controls everything.