Paul A. Clayton (paaronclayton.delete@this.gmail.com) on September 18, 2021 2:35 pm wrote:
(and if one does not have aliases in a virtually tagged cache
> one can defer translation until time to access a memory-side cache or later with the obvious benefit
> of permissions being smaller (and potentially coarser-grained) than translations).

That's only possible with single-threading systems or systems without memory coherence. There is aliases in same virtual address space if there's many cores running same process with ability to share memory concurrently in different caches. Those aliases need also solved and serialize accesses to being able retain memory coherence. To do that for many virtual address spaces cpu's memory coherence system needs to translate all memory mappings to one address space - it can be some other than physical layer if for some reason has to be(protection against side-channels...)