Michael S (already5chosen.delete@this.yahoo.com) on September 18, 2021 4:14 pm wrote:
> With permission coarser-grained than translation how are you going to emulate a Present bit in PTE?
> Or do you propose to totally give up on demand paging?

You can have additional checks on cache miss. Permission to access a cache line does not guarantee success. (You could still have an ECC failure, for example.)

Even a conventional TLB design has to deal with post-TLB failures. For example, a cache miss could race with a TLB shootdown. Or an access could have to be aborted after an earlier access faults.

The purpose of the PLB is to regulate access to virtually-cached data. If an access misses in the virtual cache layers, the miss handler may do whatever it likes. Including, presumably, address translation, but it may fail the access for any reason it likes.