By: Andrey (andrey.semashev.delete@this.gmail.com), September 10, 2021 10:38 am
Room: Moderated Discussions
Andrei F (andrei.delete@this.anandtech.com) on September 10, 2021 10:31 am wrote:
> inteluser (inteluser.delete@this.sharklasers.com) on September 10, 2021 2:52 am wrote:
> > on alder lake, how will the separation instructions of small cores or big cores?
> > will there be a dispatcher or scheduler from HW or the OS to take priority?
>
> The same way we've had heterogeneous cores in mobile SoCs for the better part of a decade.
>
> The OS scheduler just sees another core, and there's extra load and utilisation heuristics
> to schedule workloads around the various cores to make best use of perf or efficiency.
>
> There is no hardware involved.
I thought Thread Director is the hardware that is involved. It's supposed to hint the software as to where the workload is better scheduled.
> inteluser (inteluser.delete@this.sharklasers.com) on September 10, 2021 2:52 am wrote:
> > on alder lake, how will the separation instructions of small cores or big cores?
> > will there be a dispatcher or scheduler from HW or the OS to take priority?
>
> The same way we've had heterogeneous cores in mobile SoCs for the better part of a decade.
>
> The OS scheduler just sees another core, and there's extra load and utilisation heuristics
> to schedule workloads around the various cores to make best use of perf or efficiency.
>
> There is no hardware involved.
I thought Thread Director is the hardware that is involved. It's supposed to hint the software as to where the workload is better scheduled.
| Topic | Posted By | Date |
|---|---|---|
| alder lake. | inteluser | 2021/09/10 02:52 AM |
| alder lake. | Andrei F | 2021/09/10 10:31 AM |
| alder lake. | Andrey | 2021/09/10 10:38 AM |
| alder lake. | rwessel | 2021/09/10 12:18 PM |
| alder lake. | Andrei F | 2021/09/10 01:49 PM |
| alder lake. | Andrey | 2021/09/10 05:12 PM |
| alder lake. | David Hess | 2021/09/10 08:39 PM |
| alder lake. | Andrey | 2021/09/11 01:28 AM |
| alder lake. | --- | 2021/09/10 06:24 PM |
| alder lake. | Andrei F | 2021/09/12 02:09 AM |
| DVFS | David Kanter | 2021/09/12 10:58 PM |
| DVFS | Andrei F | 2021/09/13 02:02 AM |
| DVFS | Anon | 2021/09/13 04:28 AM |
| DVFS | Jukka Larja | 2021/09/13 06:35 AM |
| DVFS | Andrei F | 2021/09/14 01:07 AM |
| DVFS | Jukka Larja | 2021/09/14 05:11 AM |
| DVFS | Andrei F | 2021/09/14 08:55 AM |
| DVFS | Jukka Larja | 2021/09/14 11:23 AM |
| DVFS | --- | 2021/09/13 11:19 AM |
| DVFS | Doug S | 2021/09/13 11:57 AM |
| DVFS | David Hess | 2021/09/13 12:32 PM |
| DVFS | --- | 2021/09/13 02:06 PM |
| DVFS | David Hess | 2021/09/13 03:21 PM |
| DVFS | David Kanter | 2021/09/15 04:05 PM |
| DVFS | David Hess | 2021/09/13 12:46 PM |
| DVFS | Jukka Larja | 2021/09/14 05:35 AM |
| Quick shutdown? | David Kanter | 2021/09/15 11:46 AM |
| Quick shutdown? | Andrei F | 2021/09/16 08:12 AM |
| Quick shutdown? | David Kanter | 2021/09/16 12:04 PM |
| Quick shutdown? | Andrei F | 2021/09/17 02:35 AM |
| Quick shutdown? | Andrei F | 2021/09/17 02:38 AM |
| and weren't 'they' right? | Daniel B | 2021/09/13 05:20 AM |
| and weren't 'they' right? | Andrei F | 2021/09/13 05:51 AM |
| and weren't 'they' right? | Daniel B | 2021/09/13 07:29 AM |
| and weren't 'they' right? | anon | 2021/09/13 06:07 AM |
| and weren't 'they' right? | Jukka Larja | 2021/09/13 06:26 AM |
| and weren't 'they' right? | anon | 2021/09/14 12:37 AM |
| Alder Lake has no little cores | Heikki Kultala | 2021/09/13 07:33 AM |
| Alder Lake has no little cores | Michael S | 2021/09/13 08:33 AM |
| Alder Lake has no little cores | me | 2021/09/13 11:45 AM |
| Alder Lake has no little cores | Heikki Kultala | 2021/09/13 02:49 PM |
| Alder Lake has no little cores | anon | 2021/09/14 12:42 AM |
| why stop at two core sizes? | hobold | 2021/09/14 06:47 AM |
| Memory caches did this, right? | Mark Roulo | 2021/09/14 03:51 PM |
| Memory caches did this, right? | Brett | 2021/09/14 08:17 PM |
| Memory caches did this, right? | Kevin G | 2021/09/16 04:10 PM |
| Large reorder buffers (L1+L2) | ⚛ | 2021/09/15 12:24 PM |
| Large reorder buffers (L1+L2) | hobold | 2021/09/15 01:06 PM |
| Alder Lake has no little cores | Adrian | 2021/09/14 09:33 AM |
| and weren't 'they' right? | David Hess | 2021/09/13 01:00 PM |
| Battery vs Performance | Mark Roulo | 2021/09/13 01:18 PM |
| Battery vs Performance | Doug S | 2021/09/13 03:05 PM |
| Battery vs Performance | David Hess | 2021/09/13 03:28 PM |
| Battery vs Performance | --- | 2021/09/13 06:08 PM |
| Battery vs Performance | --- | 2021/09/13 06:08 PM |
| Battery vs Performance | Doug S | 2021/09/13 09:53 PM |
| Battery vs Performance | Anon | 2021/09/14 07:42 AM |
| and weren't 'they' right? | Daniel B | 2021/09/13 01:57 PM |
| and weren't 'they' right? | David Hess | 2021/09/13 03:11 PM |
| and weren't 'they' right? | --- | 2021/09/13 03:38 PM |
| and weren't 'they' right? | --- | 2021/09/13 03:32 PM |
| and weren't 'they' right? | Brendan | 2021/09/14 04:30 AM |
| and weren't 'they' right? | Jukka Larja | 2021/09/14 05:31 AM |
| and weren't 'they' right? | Etienne Lorrain | 2021/09/14 01:29 AM |