Alder Lake has no little cores

By: Michael S (already5chosen.delete@this.yahoo.com), September 13, 2021 7:33 am
Room: Moderated Discussions
Heikki Kultala (heikki.kultala.delete@this.gmail.com) on September 13, 2021 7:33 am wrote:
> Daniel B (fejenagy.delete@this.gmail.com) on September 13, 2021 5:20 am wrote:
> > Andrei F (andrei.delete@this.anandtech.com) on September 12, 2021 2:09 am wrote:
> > > --- (---.delete@this.redheron.com) on September 10, 2021 6:24 pm wrote:
> > > > Andrei F (andrei.delete@this.anandtech.com) on September 10, 2021 1:49 pm wrote:
> > > > > Andrey (andrey.semashev.delete@this.gmail.com) on September 10, 2021 10:38 am wrote:
> > > > > > Andrei F (andrei.delete@this.anandtech.com) on September 10, 2021 10:31 am wrote:
> > > > > > > inteluser (inteluser.delete@this.sharklasers.com) on September 10, 2021 2:52 am wrote:
> > > > > > > > on alder lake, how will the separation instructions of small cores or big cores?
> > > > > > > > will there be a dispatcher or scheduler from HW or the OS to take priority?
> > > > > > >
> > > > > > > The same way we've had heterogeneous cores in mobile SoCs for the better part of a decade.
> > > > > > >
> > > > > > > The OS scheduler just sees another core, and there's extra load and utilisation heuristics
> > > > > > > to schedule workloads around the various cores to make best use of perf or efficiency.
> > > > > > >
> > > > > > > There is no hardware involved.
> > > > > >
> > > > > > I thought Thread Director is the hardware that is involved. It's supposed
> > > > > > to hint the software as to where the workload is better scheduled.
> > > > > >
> > > > >
> > > > > It's just a glorified microcontroller that collects performance counter data and writes into some
> > > > > structs into memory that the OS then uses to make scheduler migration decisions. The same thing could
> > > > > be done totally in software, though with a little more overhead due to the finer granularity.
> > > >
> > > > In PRINCIPLE the HW can do more. Whether you call this "scheduling" is an uninteresing question IMHO.
> > > >
> > > > Obviously (even pre-AMP) the HW can use the indicators it tracks to vary the DVFS
> > > > of a CPU. I thought Intel already does this as one of the versions of Turboboost.
> > > >
> > > > Next you can use the indicators to dynamically vary more just
> > > > CPU performance; for example code with an aggressive
> > > > DRAM profile can have the DRAM frequency boosted to maximum even as the CPU frequency is reduced.
> > >
> > >
> > > There is no "HW" in the proper term, it's still a software firmware just that it's running
> > > on a smaller low-power microcontroller instead of the CPU cores themselves.
> > >
> > > DRAM is already a completely separate domain that is completely transparent to
> > > the OS in most parts and any serious SoC have had microcontroller targeted independent
> > > DVFS based on NoC/MC traffic. We've had this for years and years.
> > >
> > > >
> > > > Finally (and this is AMP-relevant) if a large core has a relationship with a small core
> > > > (eg producer-consumer, ...) the small core can be appropriately boosted in speed.
> > > > The one version of this (there are probably more) that we know of is a large core
> > > > tracking that some fraction of its cache misses are sourced from a small core:
> > > > https://patents.google.com/patent/US10942850B2
> > >
> > > (This isn't related to that patent but in general)
> > > One of the biggest issues that the traditional companies is that they have not understood power efficient
> > > DVFS. Years ago, Intel engineers lambasted schemes like big.LITTLE because it was "not hardware controlled"
> > > - but you precisely do not want ultra-fine grained DVFS like that for several reasons. In battery powered
> > > devices the whole point of DVFS was to avoid the higher
> > > performance states and voltages as much as possible,
> > > and what matters here is the delivery of performance within a unit of user experience, essentially a 16ms
> > > or 8ms frame, which is AGES. The act of frequency and voltage change itself takes up quite a bit of energy
> > > and you literally do not want to do it that fast because it actually would be more efficient to smooth out
> > > performance over the duration of your frame at a lower state, or clock/power-gate at smaller idle periods
> > > rather than to DVFS down. The same applies to things like DRAM frequency changes - you don't want to track
> > > and change this in a too fine-grained manner because you'll be wasting a ton of energy.
> > >
> > > Related to that Apple patent, I ask if the energy investment is worth it given
> > > it's only a "fraction" of cache misses - you're not just impacting the one small
> > > core but the whole frequency and voltage domain of the small core cluster.
> > >
> > > Alder Lake is a bit special here in that it will go both in battery powered devices as well
> > > as AC power devices - the latter is a performance scenario we haven't seen before in heterogenous
> > > CPU designs so maybe a lot of the perceptions get thrown out the window, but I have doubts
> > > that Intel will implement two completely different operation modes - we'll see.
> >
> >
> > As a self-confessed ignoramus, I still think that for the vast majority of cases going big-little is simply
> > a business case/economics decision for NRE cost/effort vs. variable cost (silicon estate), as opposed to
> > being based on technical merit. In Alderlake, I find it
> > wholly confusing why would anyone care for the little
> > cores, and why I'm paying for them.
>
> There are no little cores in Alder Lake. There are mediun cores. And these
> medium cores gives twice the performance/area than the big cores.
>

Who cares?
CPU cores, including L2, are not majority of client SoC die area. 25-30% ? Or less?

> Now there is throughput performance worth 12 big cores, but area of only 10 big cores.
>


Who cares?
Embarrassingly-parallel client workloads are very rare.


> The advantage would be even better if there was 16 instead of 8 of those medium cores.
>
> > Even in most laptops, A processor should be a small fraction of a laptop's
> > energy need, it's the screen and wifi. In a smartphone,
> > I don't get why not properly design a mid-field core,
> > rather than have high performance which most people never need, paired with low performance with may not
> > be enough often not to engage the HP core.
>
> Greacemont is exactly that medium core.
>

But I certainly don't need medium cores on desktop any more than I need little cores. Either one serves no useful purpose.
Unless it's low end cost-optimized desktop, probably in miniPC form-factor, in which case I don't need anything *but* medium cores.

> But there are lots of tasks where the best possible single thread
> performance is desired, which is why we also have the big cores.
>
>

< Previous Post in ThreadNext Post in Thread >
TopicPosted ByDate
alder lake.inteluser2021/09/10 01:52 AM
  alder lake.Andrei F2021/09/10 09:31 AM
    alder lake.Andrey2021/09/10 09:38 AM
      alder lake.rwessel2021/09/10 11:18 AM
      alder lake.Andrei F2021/09/10 12:49 PM
        alder lake.Andrey2021/09/10 04:12 PM
          alder lake.David Hess2021/09/10 07:39 PM
            alder lake.Andrey2021/09/11 12:28 AM
        alder lake.---2021/09/10 05:24 PM
          alder lake.Andrei F2021/09/12 01:09 AM
            DVFSDavid Kanter2021/09/12 09:58 PM
              DVFSAndrei F2021/09/13 01:02 AM
                DVFSAnon2021/09/13 03:28 AM
                DVFSJukka Larja2021/09/13 05:35 AM
                  DVFSAndrei F2021/09/14 12:07 AM
                    DVFSJukka Larja2021/09/14 04:11 AM
                      DVFSAndrei F2021/09/14 07:55 AM
                        DVFSJukka Larja2021/09/14 10:23 AM
                DVFS---2021/09/13 10:19 AM
                  DVFSDoug S2021/09/13 10:57 AM
                    DVFSDavid Hess2021/09/13 11:32 AM
                    DVFS---2021/09/13 01:06 PM
                      DVFSDavid Hess2021/09/13 02:21 PM
                    DVFSDavid Kanter2021/09/15 03:05 PM
                  DVFSDavid Hess2021/09/13 11:46 AM
                  DVFSJukka Larja2021/09/14 04:35 AM
                Quick shutdown?David Kanter2021/09/15 10:46 AM
                  Quick shutdown?Andrei F2021/09/16 07:12 AM
                    Quick shutdown?David Kanter2021/09/16 11:04 AM
                      Quick shutdown?Andrei F2021/09/17 01:35 AM
                        Quick shutdown?Andrei F2021/09/17 01:38 AM
            and weren't 'they' right?Daniel B2021/09/13 04:20 AM
              and weren't 'they' right?Andrei F2021/09/13 04:51 AM
                and weren't 'they' right?Daniel B2021/09/13 06:29 AM
              and weren't 'they' right?anon2021/09/13 05:07 AM
                and weren't 'they' right?Jukka Larja2021/09/13 05:26 AM
                  and weren't 'they' right?anon2021/09/13 11:37 PM
              Alder Lake has no little coresHeikki Kultala2021/09/13 06:33 AM
                Alder Lake has no little coresMichael S2021/09/13 07:33 AM
                  Alder Lake has no little coresme2021/09/13 10:45 AM
                  Alder Lake has no little coresHeikki Kultala2021/09/13 01:49 PM
                    Alder Lake has no little coresanon2021/09/13 11:42 PM
                why stop at two core sizes?hobold2021/09/14 05:47 AM
                  Memory caches did this, right?Mark Roulo2021/09/14 02:51 PM
                    Memory caches did this, right?Brett2021/09/14 07:17 PM
                      Memory caches did this, right?Kevin G2021/09/16 03:10 PM
                  Large reorder buffers (L1+L2)2021/09/15 11:24 AM
                    Large reorder buffers (L1+L2)hobold2021/09/15 12:06 PM
                Alder Lake has no little coresAdrian2021/09/14 08:33 AM
              and weren't 'they' right?David Hess2021/09/13 12:00 PM
                Battery vs PerformanceMark Roulo2021/09/13 12:18 PM
                  Battery vs PerformanceDoug S2021/09/13 02:05 PM
                    Battery vs PerformanceDavid Hess2021/09/13 02:28 PM
                      Battery vs Performance---2021/09/13 05:08 PM
                      Battery vs Performance---2021/09/13 05:08 PM
                      Battery vs PerformanceDoug S2021/09/13 08:53 PM
                    Battery vs PerformanceAnon2021/09/14 06:42 AM
                and weren't 'they' right?Daniel B2021/09/13 12:57 PM
                  and weren't 'they' right?David Hess2021/09/13 02:11 PM
                    and weren't 'they' right?---2021/09/13 02:38 PM
                  and weren't 'they' right?---2021/09/13 02:32 PM
                and weren't 'they' right?Brendan2021/09/14 03:30 AM
                  and weren't 'they' right?Jukka Larja2021/09/14 04:31 AM
              and weren't 'they' right?Etienne Lorrain2021/09/14 12:29 AM
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