DVFS

By: Doug S (foo.delete@this.bar.bar), September 13, 2021 10:57 am
Room: Moderated Discussions
--- (---.delete@this.redheron.com) on September 13, 2021 11:19 am wrote:
> - one thing Apple do (I don't know about other designs) is slide voltage up and down while keeping frequency
> unchanged. Obviously changing frequency is somewhat disruptive in a way that changing voltage is not.
> Apple have some flexibility to do this given the digital power estimators, a knowledge of the capacitance in
> the system, and an ability to prevent catastrophe if the system is oversubscribed by having instruction issue
> paused by the DPE for a cycle or two. Maybe also the fact that every SRAM is decoupled from logic with a voltage
> shifter between the two, so you have flexibility to down-voltage logic while not losing SRAM retention.
> (At least they have a long sequence of patents about this, so you'd hope it's implemented!)


I'm a little confused on this point. Why would you want to alter voltage while keeping frequency constant? Shouldn't you always want to run at the lowest voltage capable of handling a given frequency to minimize power? In what circumstance would you for example want to increase voltage while keeping frequency constant? That makes no sense to me, but maybe I'm missing something.
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TopicPosted ByDate
alder lake.inteluser2021/09/10 01:52 AM
  alder lake.Andrei F2021/09/10 09:31 AM
    alder lake.Andrey2021/09/10 09:38 AM
      alder lake.rwessel2021/09/10 11:18 AM
      alder lake.Andrei F2021/09/10 12:49 PM
        alder lake.Andrey2021/09/10 04:12 PM
          alder lake.David Hess2021/09/10 07:39 PM
            alder lake.Andrey2021/09/11 12:28 AM
        alder lake.---2021/09/10 05:24 PM
          alder lake.Andrei F2021/09/12 01:09 AM
            DVFSDavid Kanter2021/09/12 09:58 PM
              DVFSAndrei F2021/09/13 01:02 AM
                DVFSAnon2021/09/13 03:28 AM
                DVFSJukka Larja2021/09/13 05:35 AM
                  DVFSAndrei F2021/09/14 12:07 AM
                    DVFSJukka Larja2021/09/14 04:11 AM
                      DVFSAndrei F2021/09/14 07:55 AM
                        DVFSJukka Larja2021/09/14 10:23 AM
                DVFS---2021/09/13 10:19 AM
                  DVFSDoug S2021/09/13 10:57 AM
                    DVFSDavid Hess2021/09/13 11:32 AM
                    DVFS---2021/09/13 01:06 PM
                      DVFSDavid Hess2021/09/13 02:21 PM
                    DVFSDavid Kanter2021/09/15 03:05 PM
                  DVFSDavid Hess2021/09/13 11:46 AM
                  DVFSJukka Larja2021/09/14 04:35 AM
                Quick shutdown?David Kanter2021/09/15 10:46 AM
                  Quick shutdown?Andrei F2021/09/16 07:12 AM
                    Quick shutdown?David Kanter2021/09/16 11:04 AM
                      Quick shutdown?Andrei F2021/09/17 01:35 AM
                        Quick shutdown?Andrei F2021/09/17 01:38 AM
            and weren't 'they' right?Daniel B2021/09/13 04:20 AM
              and weren't 'they' right?Andrei F2021/09/13 04:51 AM
                and weren't 'they' right?Daniel B2021/09/13 06:29 AM
              and weren't 'they' right?anon2021/09/13 05:07 AM
                and weren't 'they' right?Jukka Larja2021/09/13 05:26 AM
                  and weren't 'they' right?anon2021/09/13 11:37 PM
              Alder Lake has no little coresHeikki Kultala2021/09/13 06:33 AM
                Alder Lake has no little coresMichael S2021/09/13 07:33 AM
                  Alder Lake has no little coresme2021/09/13 10:45 AM
                  Alder Lake has no little coresHeikki Kultala2021/09/13 01:49 PM
                    Alder Lake has no little coresanon2021/09/13 11:42 PM
                why stop at two core sizes?hobold2021/09/14 05:47 AM
                  Memory caches did this, right?Mark Roulo2021/09/14 02:51 PM
                    Memory caches did this, right?Brett2021/09/14 07:17 PM
                      Memory caches did this, right?Kevin G2021/09/16 03:10 PM
                  Large reorder buffers (L1+L2)2021/09/15 11:24 AM
                    Large reorder buffers (L1+L2)hobold2021/09/15 12:06 PM
                Alder Lake has no little coresAdrian2021/09/14 08:33 AM
              and weren't 'they' right?David Hess2021/09/13 12:00 PM
                Battery vs PerformanceMark Roulo2021/09/13 12:18 PM
                  Battery vs PerformanceDoug S2021/09/13 02:05 PM
                    Battery vs PerformanceDavid Hess2021/09/13 02:28 PM
                      Battery vs Performance---2021/09/13 05:08 PM
                      Battery vs Performance---2021/09/13 05:08 PM
                      Battery vs PerformanceDoug S2021/09/13 08:53 PM
                    Battery vs PerformanceAnon2021/09/14 06:42 AM
                and weren't 'they' right?Daniel B2021/09/13 12:57 PM
                  and weren't 'they' right?David Hess2021/09/13 02:11 PM
                    and weren't 'they' right?---2021/09/13 02:38 PM
                  and weren't 'they' right?---2021/09/13 02:32 PM
                and weren't 'they' right?Brendan2021/09/14 03:30 AM
                  and weren't 'they' right?Jukka Larja2021/09/14 04:31 AM
              and weren't 'they' right?Etienne Lorrain2021/09/14 12:29 AM
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