Doug S (foo.delete@this.bar.bar) on September 13, 2021 11:57 am wrote:
> --- (---.delete@this.redheron.com) on September 13, 2021 11:19 am wrote:
> > - one thing Apple do (I don't know about other designs)
> > is slide voltage up and down while keeping frequency
> > unchanged. Obviously changing frequency is somewhat disruptive in a way that changing voltage is not.
> > Apple have some flexibility to do this given the digital
> > power estimators, a knowledge of the capacitance in
> > the system, and an ability to prevent catastrophe if the
> > system is oversubscribed by having instruction issue
> > paused by the DPE for a cycle or two. Maybe also the fact
> > that every SRAM is decoupled from logic with a voltage
> > shifter between the two, so you have flexibility to down-voltage logic while not losing SRAM retention.
> > (At least they have a long sequence of patents about this, so you'd hope it's implemented!)
>
>
> I'm a little confused on this point. Why would you want to alter voltage while keeping frequency
> constant? Shouldn't you always want to run at the lowest voltage capable of handling a given frequency
> to minimize power? In what circumstance would you for example want to increase voltage while keeping
> frequency constant? That makes no sense to me, but maybe I'm missing something.
>

I'm no expert at this low-level, but I think the primary issue is voltage droop.
Obviously an ideal power source would maintain the exact (varying) current you need at the exact (unvarying) voltage you request, but the reality is that as load changes, voltage will droop.
You can either deal with this by constantly operating at a higher voltage than absolutely necessary, or you can slide voltage up-and-down reactively, as I suggested -- but the closer you operate to the edge, the faster you need to be able to cope with an unexpected additional load.

Here's an example of what I'm talking about
https://patents.google.com/patent/US20150033045A1

Here's a more explicit version
https://patents.google.com/patent/US20150253836A1
with an update a few years later here
https://patents.google.com/patent/US10401938B1
(Note as you read these the reference to, for example, micro-architectural features of the core, like a particular pipeline, being powered down, which knowledge can be used to reduce voltage margin.)

Here's a really low level version (hardly relevant to the discussion except that it's in the same philosophical vein) tracking changes, by analog means, of the retention voltages required for individual SRAM sub-arrays; and switching the feed into those arrays by having each sub-array connected to a set of slightly different diodes, the optimal one of which at any give time feeds in power.
https://patents.google.com/patent/US9792979B1


Here's an example from the other side (rather than trying to operate at minimum voltage, ensure that maximum performance is achieved, but issue throttling will kick in if too many IP blocks all simultaneously go into high power)
https://patents.google.com/patent/US20140380071A1

There are multiple of these sorts of patents, covering different cases (for example the required/desired voltage can slide up and down as system temperature changes, as the system ages, etc). Some monitoring is done by the DPE's, some by various analog circuits.


Obviously at least some of this is being done by other companies (eg Intel are monitoring which of N cores on a die have the best efficiency so that those can be goosed an extra 100MHz when no other cores are active, whatever Turboboost version that one is called).

I make no claim for the uniqueness of what Apple is doing, simply that they track the whole set of possibilities
- very slow changes (aging)
- slow (by computer standards) changes like temperature
- fast change (IP blocks powering up and powering off)
- cycle to cycle changes (DPE, and preventing issue to limit exceeding spec)
and they provide enough separate voltage planes and islands to manage this on a very fine-grained scale.