Memory caches did this, right?

By: Brett (ggtgp.delete@this.yahoo.com), September 14, 2021 8:17 pm
Room: Moderated Discussions
Mark Roulo (nothanks.delete@this.xxx.com) on September 14, 2021 3:51 pm wrote:
> hobold (hobold.delete@this.vectorizer.org) on September 14, 2021 6:47 am wrote:
> > Heikki Kultala (heikki.kultala.delete@this.gmail.com) on September 13, 2021 7:33 am wrote:
> >
> > > There are no little cores in Alder Lake. There are mediun cores. And these
> > > medium cores gives twice the performance/area than the big cores.
> > >
> > > Now there is throughput performance worth 12 big cores, but area of only 10 big cores.
> > >
> > > The advantage would be even better if there was 16 instead of 8 of those medium cores.
> >
> > Why stop there? By that line of reasoning, one would want many different core sizes
> > from big to little. Say, core N has performance proportional to 0.9^N, silicon
> > area proportional to 0.8^N, and power consumption proportional to 0.75^N.
> >
> > This way, the fewer threads are running, the faster each
> > thread gets to run. And the more runnable threads there
> > are, the more efficient the cores are getting (both in terms of energy as well as silicon real estate).
> >
> > Punch line: total silicon area and power consumption of an infinite number of such
> > cores is finite. :-) But performance is finite, too. And yes, the extreme version
> > of this idea is a joke ... but what about three, four, five ... core sizes?
> >
> > One could always shrink and re-use previous generation cores, instead of having to re-design
> > every core type from scratch. Or one could use parameterized synthesizable cores and let core
> > proliferation be a semi-automatic thing. We do have AI now to handle the bulk of grunt work.
>
> Caches seem to have played out this way.
>
> The older microprocessors didn't have caches.
>
> The z15 had L1 (I and D), L2, L3 and L4 ...
>
> If one want to think of "memory hierarchy" rather than cache we have something like:

You missed two levels:
>

    >
  1. Registers

  2. >
  3. L1 cache

  4. >
  5. L2 cache

  6. >
  7. L3 cache

  8. >
  9. L4 cache (on z15 anyway)

  10. >
  11. DRAM


  12. Compressed memory

  13. Flash


  14. >
  15. Disk for paging (HDD or SSD)

  16. >
  17. Tape

  18. >

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TopicPosted ByDate
alder lake.inteluser2021/09/10 02:52 AM
  alder lake.Andrei F2021/09/10 10:31 AM
    alder lake.Andrey2021/09/10 10:38 AM
      alder lake.rwessel2021/09/10 12:18 PM
      alder lake.Andrei F2021/09/10 01:49 PM
        alder lake.Andrey2021/09/10 05:12 PM
          alder lake.David Hess2021/09/10 08:39 PM
            alder lake.Andrey2021/09/11 01:28 AM
        alder lake.---2021/09/10 06:24 PM
          alder lake.Andrei F2021/09/12 02:09 AM
            DVFSDavid Kanter2021/09/12 10:58 PM
              DVFSAndrei F2021/09/13 02:02 AM
                DVFSAnon2021/09/13 04:28 AM
                DVFSJukka Larja2021/09/13 06:35 AM
                  DVFSAndrei F2021/09/14 01:07 AM
                    DVFSJukka Larja2021/09/14 05:11 AM
                      DVFSAndrei F2021/09/14 08:55 AM
                        DVFSJukka Larja2021/09/14 11:23 AM
                DVFS---2021/09/13 11:19 AM
                  DVFSDoug S2021/09/13 11:57 AM
                    DVFSDavid Hess2021/09/13 12:32 PM
                    DVFS---2021/09/13 02:06 PM
                      DVFSDavid Hess2021/09/13 03:21 PM
                    DVFSDavid Kanter2021/09/15 04:05 PM
                  DVFSDavid Hess2021/09/13 12:46 PM
                  DVFSJukka Larja2021/09/14 05:35 AM
                Quick shutdown?David Kanter2021/09/15 11:46 AM
                  Quick shutdown?Andrei F2021/09/16 08:12 AM
                    Quick shutdown?David Kanter2021/09/16 12:04 PM
                      Quick shutdown?Andrei F2021/09/17 02:35 AM
                        Quick shutdown?Andrei F2021/09/17 02:38 AM
            and weren't 'they' right?Daniel B2021/09/13 05:20 AM
              and weren't 'they' right?Andrei F2021/09/13 05:51 AM
                and weren't 'they' right?Daniel B2021/09/13 07:29 AM
              and weren't 'they' right?anon2021/09/13 06:07 AM
                and weren't 'they' right?Jukka Larja2021/09/13 06:26 AM
                  and weren't 'they' right?anon2021/09/14 12:37 AM
              Alder Lake has no little coresHeikki Kultala2021/09/13 07:33 AM
                Alder Lake has no little coresMichael S2021/09/13 08:33 AM
                  Alder Lake has no little coresme2021/09/13 11:45 AM
                  Alder Lake has no little coresHeikki Kultala2021/09/13 02:49 PM
                    Alder Lake has no little coresanon2021/09/14 12:42 AM
                why stop at two core sizes?hobold2021/09/14 06:47 AM
                  Memory caches did this, right?Mark Roulo2021/09/14 03:51 PM
                    Memory caches did this, right?Brett2021/09/14 08:17 PM
                      Memory caches did this, right?Kevin G2021/09/16 04:10 PM
                  Large reorder buffers (L1+L2)2021/09/15 12:24 PM
                    Large reorder buffers (L1+L2)hobold2021/09/15 01:06 PM
                Alder Lake has no little coresAdrian2021/09/14 09:33 AM
              and weren't 'they' right?David Hess2021/09/13 01:00 PM
                Battery vs PerformanceMark Roulo2021/09/13 01:18 PM
                  Battery vs PerformanceDoug S2021/09/13 03:05 PM
                    Battery vs PerformanceDavid Hess2021/09/13 03:28 PM
                      Battery vs Performance---2021/09/13 06:08 PM
                      Battery vs Performance---2021/09/13 06:08 PM
                      Battery vs PerformanceDoug S2021/09/13 09:53 PM
                    Battery vs PerformanceAnon2021/09/14 07:42 AM
                and weren't 'they' right?Daniel B2021/09/13 01:57 PM
                  and weren't 'they' right?David Hess2021/09/13 03:11 PM
                    and weren't 'they' right?---2021/09/13 03:38 PM
                  and weren't 'they' right?---2021/09/13 03:32 PM
                and weren't 'they' right?Brendan2021/09/14 04:30 AM
                  and weren't 'they' right?Jukka Larja2021/09/14 05:31 AM
              and weren't 'they' right?Etienne Lorrain2021/09/14 01:29 AM
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