By: Brett (ggtgp.delete@this.yahoo.com), September 14, 2021 7:17 pm
Room: Moderated Discussions
Mark Roulo (nothanks.delete@this.xxx.com) on September 14, 2021 3:51 pm wrote:
> hobold (hobold.delete@this.vectorizer.org) on September 14, 2021 6:47 am wrote:
> > Heikki Kultala (heikki.kultala.delete@this.gmail.com) on September 13, 2021 7:33 am wrote:
> >
> > > There are no little cores in Alder Lake. There are mediun cores. And these
> > > medium cores gives twice the performance/area than the big cores.
> > >
> > > Now there is throughput performance worth 12 big cores, but area of only 10 big cores.
> > >
> > > The advantage would be even better if there was 16 instead of 8 of those medium cores.
> >
> > Why stop there? By that line of reasoning, one would want many different core sizes
> > from big to little. Say, core N has performance proportional to 0.9^N, silicon
> > area proportional to 0.8^N, and power consumption proportional to 0.75^N.
> >
> > This way, the fewer threads are running, the faster each
> > thread gets to run. And the more runnable threads there
> > are, the more efficient the cores are getting (both in terms of energy as well as silicon real estate).
> >
> > Punch line: total silicon area and power consumption of an infinite number of such
> > cores is finite. :-) But performance is finite, too. And yes, the extreme version
> > of this idea is a joke ... but what about three, four, five ... core sizes?
> >
> > One could always shrink and re-use previous generation cores, instead of having to re-design
> > every core type from scratch. Or one could use parameterized synthesizable cores and let core
> > proliferation be a semi-automatic thing. We do have AI now to handle the bulk of grunt work.
>
> Caches seem to have played out this way.
>
> The older microprocessors didn't have caches.
>
> The z15 had L1 (I and D), L2, L3 and L4 ...
>
> If one want to think of "memory hierarchy" rather than cache we have something like:
You missed two levels:
>
> hobold (hobold.delete@this.vectorizer.org) on September 14, 2021 6:47 am wrote:
> > Heikki Kultala (heikki.kultala.delete@this.gmail.com) on September 13, 2021 7:33 am wrote:
> >
> > > There are no little cores in Alder Lake. There are mediun cores. And these
> > > medium cores gives twice the performance/area than the big cores.
> > >
> > > Now there is throughput performance worth 12 big cores, but area of only 10 big cores.
> > >
> > > The advantage would be even better if there was 16 instead of 8 of those medium cores.
> >
> > Why stop there? By that line of reasoning, one would want many different core sizes
> > from big to little. Say, core N has performance proportional to 0.9^N, silicon
> > area proportional to 0.8^N, and power consumption proportional to 0.75^N.
> >
> > This way, the fewer threads are running, the faster each
> > thread gets to run. And the more runnable threads there
> > are, the more efficient the cores are getting (both in terms of energy as well as silicon real estate).
> >
> > Punch line: total silicon area and power consumption of an infinite number of such
> > cores is finite. :-) But performance is finite, too. And yes, the extreme version
> > of this idea is a joke ... but what about three, four, five ... core sizes?
> >
> > One could always shrink and re-use previous generation cores, instead of having to re-design
> > every core type from scratch. Or one could use parameterized synthesizable cores and let core
> > proliferation be a semi-automatic thing. We do have AI now to handle the bulk of grunt work.
>
> Caches seem to have played out this way.
>
> The older microprocessors didn't have caches.
>
> The z15 had L1 (I and D), L2, L3 and L4 ...
>
> If one want to think of "memory hierarchy" rather than cache we have something like:
You missed two levels:
>
- Registers
- L1 cache
- L2 cache
- L3 cache
- L4 cache (on z15 anyway)
- DRAM
- Compressed memory
- Flash
- Disk for paging (HDD or SSD)
- Tape
>
>
>
>
>
>
>
>
>
Topic | Posted By | Date |
---|---|---|
alder lake. | inteluser | 2021/09/10 01:52 AM |
alder lake. | Andrei F | 2021/09/10 09:31 AM |
alder lake. | Andrey | 2021/09/10 09:38 AM |
alder lake. | rwessel | 2021/09/10 11:18 AM |
alder lake. | Andrei F | 2021/09/10 12:49 PM |
alder lake. | Andrey | 2021/09/10 04:12 PM |
alder lake. | David Hess | 2021/09/10 07:39 PM |
alder lake. | Andrey | 2021/09/11 12:28 AM |
alder lake. | --- | 2021/09/10 05:24 PM |
alder lake. | Andrei F | 2021/09/12 01:09 AM |
DVFS | David Kanter | 2021/09/12 09:58 PM |
DVFS | Andrei F | 2021/09/13 01:02 AM |
DVFS | Anon | 2021/09/13 03:28 AM |
DVFS | Jukka Larja | 2021/09/13 05:35 AM |
DVFS | Andrei F | 2021/09/14 12:07 AM |
DVFS | Jukka Larja | 2021/09/14 04:11 AM |
DVFS | Andrei F | 2021/09/14 07:55 AM |
DVFS | Jukka Larja | 2021/09/14 10:23 AM |
DVFS | --- | 2021/09/13 10:19 AM |
DVFS | Doug S | 2021/09/13 10:57 AM |
DVFS | David Hess | 2021/09/13 11:32 AM |
DVFS | --- | 2021/09/13 01:06 PM |
DVFS | David Hess | 2021/09/13 02:21 PM |
DVFS | David Kanter | 2021/09/15 03:05 PM |
DVFS | David Hess | 2021/09/13 11:46 AM |
DVFS | Jukka Larja | 2021/09/14 04:35 AM |
Quick shutdown? | David Kanter | 2021/09/15 10:46 AM |
Quick shutdown? | Andrei F | 2021/09/16 07:12 AM |
Quick shutdown? | David Kanter | 2021/09/16 11:04 AM |
Quick shutdown? | Andrei F | 2021/09/17 01:35 AM |
Quick shutdown? | Andrei F | 2021/09/17 01:38 AM |
and weren't 'they' right? | Daniel B | 2021/09/13 04:20 AM |
and weren't 'they' right? | Andrei F | 2021/09/13 04:51 AM |
and weren't 'they' right? | Daniel B | 2021/09/13 06:29 AM |
and weren't 'they' right? | anon | 2021/09/13 05:07 AM |
and weren't 'they' right? | Jukka Larja | 2021/09/13 05:26 AM |
and weren't 'they' right? | anon | 2021/09/13 11:37 PM |
Alder Lake has no little cores | Heikki Kultala | 2021/09/13 06:33 AM |
Alder Lake has no little cores | Michael S | 2021/09/13 07:33 AM |
Alder Lake has no little cores | me | 2021/09/13 10:45 AM |
Alder Lake has no little cores | Heikki Kultala | 2021/09/13 01:49 PM |
Alder Lake has no little cores | anon | 2021/09/13 11:42 PM |
why stop at two core sizes? | hobold | 2021/09/14 05:47 AM |
Memory caches did this, right? | Mark Roulo | 2021/09/14 02:51 PM |
Memory caches did this, right? | Brett | 2021/09/14 07:17 PM |
Memory caches did this, right? | Kevin G | 2021/09/16 03:10 PM |
Large reorder buffers (L1+L2) | ⚛ | 2021/09/15 11:24 AM |
Large reorder buffers (L1+L2) | hobold | 2021/09/15 12:06 PM |
Alder Lake has no little cores | Adrian | 2021/09/14 08:33 AM |
and weren't 'they' right? | David Hess | 2021/09/13 12:00 PM |
Battery vs Performance | Mark Roulo | 2021/09/13 12:18 PM |
Battery vs Performance | Doug S | 2021/09/13 02:05 PM |
Battery vs Performance | David Hess | 2021/09/13 02:28 PM |
Battery vs Performance | --- | 2021/09/13 05:08 PM |
Battery vs Performance | --- | 2021/09/13 05:08 PM |
Battery vs Performance | Doug S | 2021/09/13 08:53 PM |
Battery vs Performance | Anon | 2021/09/14 06:42 AM |
and weren't 'they' right? | Daniel B | 2021/09/13 12:57 PM |
and weren't 'they' right? | David Hess | 2021/09/13 02:11 PM |
and weren't 'they' right? | --- | 2021/09/13 02:38 PM |
and weren't 'they' right? | --- | 2021/09/13 02:32 PM |
and weren't 'they' right? | Brendan | 2021/09/14 03:30 AM |
and weren't 'they' right? | Jukka Larja | 2021/09/14 04:31 AM |
and weren't 'they' right? | Etienne Lorrain | 2021/09/14 12:29 AM |