hobold (hobold.delete@this.vectorizer.org) on September 14, 2021 6:47 am wrote:
> Heikki Kultala (heikki.kultala.delete@this.gmail.com) on September 13, 2021 7:33 am wrote:
>
> > There are no little cores in Alder Lake. There are mediun cores. And these
> > medium cores gives twice the performance/area than the big cores.
> >
> > Now there is throughput performance worth 12 big cores, but area of only 10 big cores.
> >
> > The advantage would be even better if there was 16 instead of 8 of those medium cores.
>
> Why stop there? By that line of reasoning, one would want many different core sizes
> from big to little. Say, core N has performance proportional to 0.9^N, silicon
> area proportional to 0.8^N, and power consumption proportional to 0.75^N.
>
> This way, the fewer threads are running, the faster each thread gets to run. And the more runnable threads there
> are, the more efficient the cores are getting (both in terms of energy as well as silicon real estate).
>
> Punch line: total silicon area and power consumption of an infinite number of such
> cores is finite. :-) But performance is finite, too. And yes, the extreme version
> of this idea is a joke ... but what about three, four, five ... core sizes?

I question that three core sizes in a single CPU will be able to make sense once the reorder buffer (RB) in a future P-core is split into L1 RB (for example: 128 or 256 entries) and L2 RB (for example: 4096 entries), because the performance disparity between the 1st core size (with L1+L2 RB) and the 3rd core size (with just L1 RB) in a CPU with 3 different core sizes would be too large (that is: the performance would differ by a factor of 10).

-atom