⚛ (0xe2.0x9a.0x9b.delete@this.gmail.com) on September 15, 2021 12:24 pm wrote:
[...]
> I question that three core sizes in a single CPU will be able to make sense once the reorder
> buffer (RB) in a future P-core is split into L1 RB (for example: 128 or 256 entries) and
> L2 RB (for example: 4096 entries), because the performance disparity between the 1st core
> size (with L1+L2 RB) and the 3rd core size (with just L1 RB) in a CPU with 3 different core
> sizes would be too large (that is: the performance would differ by a factor of 10).

The re-order buffer is, in its most fundamental function, a queue. I am unsure where the benefit is in splitting it into two queues (a small fast one including the head, and a much larger slower one for the rest including the tail, I presume).

Is the assumption here that the tail queue is usually empty, and only gets used to continue progressing into _very_ long latency delays (and that slow progress is better than no progress)?

It seems to me it would require godly/omniscient prediction accuracy to speculate that far.