Large reorder buffers (L1+L2)

By: hobold (hobold.delete@this.vectorizer.org), September 15, 2021 1:06 pm
Room: Moderated Discussions
⚛ (0xe2.0x9a.0x9b.delete@this.gmail.com) on September 15, 2021 12:24 pm wrote:
[...]
> I question that three core sizes in a single CPU will be able to make sense once the reorder
> buffer (RB) in a future P-core is split into L1 RB (for example: 128 or 256 entries) and
> L2 RB (for example: 4096 entries), because the performance disparity between the 1st core
> size (with L1+L2 RB) and the 3rd core size (with just L1 RB) in a CPU with 3 different core
> sizes would be too large (that is: the performance would differ by a factor of 10).

The re-order buffer is, in its most fundamental function, a queue. I am unsure where the benefit is in splitting it into two queues (a small fast one including the head, and a much larger slower one for the rest including the tail, I presume).

Is the assumption here that the tail queue is usually empty, and only gets used to continue progressing into _very_ long latency delays (and that slow progress is better than no progress)?

It seems to me it would require godly/omniscient prediction accuracy to speculate that far.
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alder lake.inteluser2021/09/10 02:52 AM
  alder lake.Andrei F2021/09/10 10:31 AM
    alder lake.Andrey2021/09/10 10:38 AM
      alder lake.rwessel2021/09/10 12:18 PM
      alder lake.Andrei F2021/09/10 01:49 PM
        alder lake.Andrey2021/09/10 05:12 PM
          alder lake.David Hess2021/09/10 08:39 PM
            alder lake.Andrey2021/09/11 01:28 AM
        alder lake.---2021/09/10 06:24 PM
          alder lake.Andrei F2021/09/12 02:09 AM
            DVFSDavid Kanter2021/09/12 10:58 PM
              DVFSAndrei F2021/09/13 02:02 AM
                DVFSAnon2021/09/13 04:28 AM
                DVFSJukka Larja2021/09/13 06:35 AM
                  DVFSAndrei F2021/09/14 01:07 AM
                    DVFSJukka Larja2021/09/14 05:11 AM
                      DVFSAndrei F2021/09/14 08:55 AM
                        DVFSJukka Larja2021/09/14 11:23 AM
                DVFS---2021/09/13 11:19 AM
                  DVFSDoug S2021/09/13 11:57 AM
                    DVFSDavid Hess2021/09/13 12:32 PM
                    DVFS---2021/09/13 02:06 PM
                      DVFSDavid Hess2021/09/13 03:21 PM
                    DVFSDavid Kanter2021/09/15 04:05 PM
                  DVFSDavid Hess2021/09/13 12:46 PM
                  DVFSJukka Larja2021/09/14 05:35 AM
                Quick shutdown?David Kanter2021/09/15 11:46 AM
                  Quick shutdown?Andrei F2021/09/16 08:12 AM
                    Quick shutdown?David Kanter2021/09/16 12:04 PM
                      Quick shutdown?Andrei F2021/09/17 02:35 AM
                        Quick shutdown?Andrei F2021/09/17 02:38 AM
            and weren't 'they' right?Daniel B2021/09/13 05:20 AM
              and weren't 'they' right?Andrei F2021/09/13 05:51 AM
                and weren't 'they' right?Daniel B2021/09/13 07:29 AM
              and weren't 'they' right?anon2021/09/13 06:07 AM
                and weren't 'they' right?Jukka Larja2021/09/13 06:26 AM
                  and weren't 'they' right?anon2021/09/14 12:37 AM
              Alder Lake has no little coresHeikki Kultala2021/09/13 07:33 AM
                Alder Lake has no little coresMichael S2021/09/13 08:33 AM
                  Alder Lake has no little coresme2021/09/13 11:45 AM
                  Alder Lake has no little coresHeikki Kultala2021/09/13 02:49 PM
                    Alder Lake has no little coresanon2021/09/14 12:42 AM
                why stop at two core sizes?hobold2021/09/14 06:47 AM
                  Memory caches did this, right?Mark Roulo2021/09/14 03:51 PM
                    Memory caches did this, right?Brett2021/09/14 08:17 PM
                      Memory caches did this, right?Kevin G2021/09/16 04:10 PM
                  Large reorder buffers (L1+L2)2021/09/15 12:24 PM
                    Large reorder buffers (L1+L2)hobold2021/09/15 01:06 PM
                Alder Lake has no little coresAdrian2021/09/14 09:33 AM
              and weren't 'they' right?David Hess2021/09/13 01:00 PM
                Battery vs PerformanceMark Roulo2021/09/13 01:18 PM
                  Battery vs PerformanceDoug S2021/09/13 03:05 PM
                    Battery vs PerformanceDavid Hess2021/09/13 03:28 PM
                      Battery vs Performance---2021/09/13 06:08 PM
                      Battery vs Performance---2021/09/13 06:08 PM
                      Battery vs PerformanceDoug S2021/09/13 09:53 PM
                    Battery vs PerformanceAnon2021/09/14 07:42 AM
                and weren't 'they' right?Daniel B2021/09/13 01:57 PM
                  and weren't 'they' right?David Hess2021/09/13 03:11 PM
                    and weren't 'they' right?---2021/09/13 03:38 PM
                  and weren't 'they' right?---2021/09/13 03:32 PM
                and weren't 'they' right?Brendan2021/09/14 04:30 AM
                  and weren't 'they' right?Jukka Larja2021/09/14 05:31 AM
              and weren't 'they' right?Etienne Lorrain2021/09/14 01:29 AM
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