By: Doug S (foo.delete@this.bar.bar), September 16, 2021 10:57 pm
Room: Moderated Discussions
anonymou5 (no.delete@this.spam.com) on September 16, 2021 3:25 pm wrote:
> https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-a-profile-architecture-developments-2021
>
> memcpy, non-maskable interrupts, PMU updates, hinted conditional branches, and other goodies
It is easy to declare instructions for memcpy(). The devil is in the details of the implementation. How long did it take Intel to get it even halfway right?
I'll be curious to see who attempts to tackle this in an actual design, and how well such implementations hold up when Linus inevitably subjects it to some experimentation and looks for its glass jaw scenarios.
> https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-a-profile-architecture-developments-2021
>
> memcpy, non-maskable interrupts, PMU updates, hinted conditional branches, and other goodies
It is easy to declare instructions for memcpy(). The devil is in the details of the implementation. How long did it take Intel to get it even halfway right?
I'll be curious to see who attempts to tackle this in an actual design, and how well such implementations hold up when Linus inevitably subjects it to some experimentation and looks for its glass jaw scenarios.
