By: Dummond D. Slow (mental.delete@this.protozoa.us), September 25, 2021 12:52 pm
Room: Moderated Discussions
Richard S (rsa73.delete@this.iinet.net.au) on September 25, 2021 1:51 am wrote:
> --- (---.delete@this.redheron.com) on September 24, 2021 7:06 pm wrote:
> >
> > In other words, I'm not yet convinced that the A15 represents any sort of intrinsic slow-down in core design
>
> I must be the only person impressed with a 7%-11%'ish speedup in integer workloads
> on what appears to be the same, or substantially similar process.
If it is just due to a 200 and 250 MHc clockspeed boost, then not really, everybody can do that unless the previous generation was already all the way to the clock ceiling.
The raised clock might have even been possible on the past generation possibly. Perhaps they just pushed the silicon into more uncomfortable spot on the voltage curve.
>
> Especially given in the time this was being designed the M1 was finishing,
> the M2 or whatever the next generation was all happening as well.
> --- (---.delete@this.redheron.com) on September 24, 2021 7:06 pm wrote:
> >
> > In other words, I'm not yet convinced that the A15 represents any sort of intrinsic slow-down in core design
>
> I must be the only person impressed with a 7%-11%'ish speedup in integer workloads
> on what appears to be the same, or substantially similar process.
If it is just due to a 200 and 250 MHc clockspeed boost, then not really, everybody can do that unless the previous generation was already all the way to the clock ceiling.
The raised clock might have even been possible on the past generation possibly. Perhaps they just pushed the silicon into more uncomfortable spot on the voltage curve.
>
> Especially given in the time this was being designed the M1 was finishing,
> the M2 or whatever the next generation was all happening as well.
