Dummond D. Slow (mental.delete@this.protozoa.us) on September 25, 2021 12:52 pm wrote:
> Richard S (rsa73.delete@this.iinet.net.au) on September 25, 2021 1:51 am wrote:
> > --- (---.delete@this.redheron.com) on September 24, 2021 7:06 pm wrote:
> > >
> > > In other words, I'm not yet convinced that the A15 represents any sort of intrinsic slow-down in core design
> >
> > I must be the only person impressed with a 7%-11%'ish speedup in integer workloads
> > on what appears to be the same, or substantially similar process.
>
> If it is just due to a 200 and 250 MHc clockspeed boost, then not really, everybody can
> do that unless the previous generation was already all the way to the clock ceiling.
>
> The raised clock might have even been possible on the past generation possibly. Perhaps
> they just pushed the silicon into more uncomfortable spot on the voltage curve.

We'll have to see the more sophisticated analyses of reviewers like AnandTech.
But all indications are that you do Apple a disservice by claiming this is "merely" a 200MHz speed boost; it is a frequency boost yes, but apparently coupled to better energy efficiency.

A common theme through all reviews of the new iPhones is how much longer battery life they provide. Some of the specialized improvements might be the result of better functional DMA (especially the dramatically improved streaming video result) but across all reviewers one sees this same pattern of noticeably improved battery life.
Slightly more technical is the point I made that the GB5 MT result reflects not exactly a higher IPC small core but rather a SoC that is no longer thermally throttled even when all 6 cores are maxing out.

So yes, anyone can boost frequency. But doing so while reducing power, while not changing the process much, and not changing the micro-architecture much or at all, is rather less trivial!
TSMC's number for N5P vs N5 is 7% faster at iso-power. Apple seem to not wasted any of that process boost, and been able to improve various energy aspects of the SoC and (apparently) at least the thermal behavior of the cores at highest performance.

https://twitter.com/dylan522p/status/1438589502147211264

Given this apparent physical optimization, it will be interesting to see the size. Naive scaling would put it at 15/11.8*88 mm^2, ie 112 mm^2. N5P does not boast of process improved density. My expectation is we will see somewhat smaller than this 112 because the same physical optimization that allowed for lower energy can also allow for better process usage and density optimization. We'll see -- should have the chip size in a week or two.
Preliminary numbers (Tech Insights) suggest the chip size is 107.7mm^2, but I can't tell if that's their final number or an estimate based on a not-yet-decapped package;