By: NoSpammer (no.delete@this.spam.com), September 29, 2021 3:53 am
Room: Moderated Discussions
dmcq (dmcq.delete@this.fano.co.uk) on September 28, 2021 2:21 pm wrote:
> The bits could vary between implementations so letting designers optimise better. More conditions
> could be saved. The only problem I can see is big-little systems and they could just zero the bits
> if moving between different cores - with the current system how can we tell if the form optimised
> by one is okay for the other? And yes it seems like an unnecessary waste of opcodes and code space.
I think 3 instructions make very simple implementations possible for the low-end. Per example:
Initial instruction is movsb until aligned or end.
Middle instruction is movs[your core's biggest R/W chunk]
End instruction is movsb until end.
Why have more state when the state can already be in the registers and PC?
> The bits could vary between implementations so letting designers optimise better. More conditions
> could be saved. The only problem I can see is big-little systems and they could just zero the bits
> if moving between different cores - with the current system how can we tell if the form optimised
> by one is okay for the other? And yes it seems like an unnecessary waste of opcodes and code space.
I think 3 instructions make very simple implementations possible for the low-end. Per example:
Initial instruction is movsb until aligned or end.
Middle instruction is movs[your core's biggest R/W chunk]
End instruction is movsb until end.
Why have more state when the state can already be in the registers and PC?