By: Doug S (foo.delete@this.bar.bar), September 30, 2021 9:48 am
Room: Moderated Discussions
rwessel (rwessel.delete@this.yahoo.com) on September 29, 2021 11:22 pm wrote:
> Certainly. But I still don't see the point of the separate setup and finalize instructions - detecting
> those conditions is trivial (if the destination address has any low bits set, do "first", if you've fallen
> out of the "middle" loop, and the length is not zero, do a "last"). Internalizing that stuff would probably
> make it easier to sneak up on page boundaries as well, at least for simpler implementations.
Sure detecting that stuff is trivial, but they would effectively be three separate operations internally as you outline. So why not make that explicit and reduce the amount of state you have to carry when the operation is interrupted?
This is still in theory a RISC ISA after all, even though John Cocke might have considered these instructions (whether one or three) an immediate disqualification from being considered as such :)
> Certainly. But I still don't see the point of the separate setup and finalize instructions - detecting
> those conditions is trivial (if the destination address has any low bits set, do "first", if you've fallen
> out of the "middle" loop, and the length is not zero, do a "last"). Internalizing that stuff would probably
> make it easier to sneak up on page boundaries as well, at least for simpler implementations.
Sure detecting that stuff is trivial, but they would effectively be three separate operations internally as you outline. So why not make that explicit and reduce the amount of state you have to carry when the operation is interrupted?
This is still in theory a RISC ISA after all, even though John Cocke might have considered these instructions (whether one or three) an immediate disqualification from being considered as such :)
