By: rwessel (rwessel.delete@this.yahoo.com), October 3, 2021 10:51 am
Room: Moderated Discussions
Doug S (foo.delete@this.bar.bar) on October 3, 2021 10:09 am wrote:
>
> If there was an intersection between page size/range of an OS and row/column model of DRAM addressing,
> which obviously there is not, the dream solution would be to stop refreshing those pages until
> they get used as you'd get zeroing "for free" along with a bit of power savings!
Even ignoring the addressing issues, that wouldn't really work. Individual DRAM cells can persist for seconds, so you're not going to get a reliable clear without a really long wait.
>
> If there was an intersection between page size/range of an OS and row/column model of DRAM addressing,
> which obviously there is not, the dream solution would be to stop refreshing those pages until
> they get used as you'd get zeroing "for free" along with a bit of power savings!
Even ignoring the addressing issues, that wouldn't really work. Individual DRAM cells can persist for seconds, so you're not going to get a reliable clear without a really long wait.
