By: Andrey (andrey.semashev.delete@this.gmail.com), October 4, 2021 6:04 am
Room: Moderated Discussions
Etienne Lorrain (etienne_lorrain.delete@this.yahoo.fr) on October 4, 2021 5:08 am wrote:
> anon2 (anon.delete@this.anon.com) on October 3, 2021 7:58 pm wrote:
> > Why? Zeroing at the point of use means you can skip the DRAM step entirely.
> > You save one store to DRAM, and possibly even one load from DRAM.
>
> Do processors (and memory cache systems) already have the optimisation "I detected I
> am writing the complete cache line, no need to read it (maybe from DRAM), I can acquire
> the cacheline for write (as opposed to read-and-acquire the cacheline for write)"?
Sort of.
https://travisdowns.github.io/blog/2020/05/13/intel-zero-opt.html
https://travisdowns.github.io/blog/2020/05/18/icelake-zero-opt.html
> anon2 (anon.delete@this.anon.com) on October 3, 2021 7:58 pm wrote:
> > Why? Zeroing at the point of use means you can skip the DRAM step entirely.
> > You save one store to DRAM, and possibly even one load from DRAM.
>
> Do processors (and memory cache systems) already have the optimisation "I detected I
> am writing the complete cache line, no need to read it (maybe from DRAM), I can acquire
> the cacheline for write (as opposed to read-and-acquire the cacheline for write)"?
Sort of.
https://travisdowns.github.io/blog/2020/05/13/intel-zero-opt.html
https://travisdowns.github.io/blog/2020/05/18/icelake-zero-opt.html
