Etienne Lorrain (etienne_lorrain.delete@this.yahoo.fr) on October 4, 2021 5:08 am wrote:
> anon2 (anon.delete@this.anon.com) on October 3, 2021 7:58 pm wrote:
> > Why? Zeroing at the point of use means you can skip the DRAM step entirely.
> > You save one store to DRAM, and possibly even one load from DRAM.
>
> Do processors (and memory cache systems) already have the optimisation "I detected I
> am writing the complete cache line, no need to read it (maybe from DRAM), I can acquire
> the cacheline for write (as opposed to read-and-acquire the cacheline for write)"?

Some appear to under some conditions. That is why I say the extra load from DRAM is a possibility not a certainty. But even in that case you do have to load from DRAM in order to write back the stores into cache, at least the DRAM loads are not blocking execution because those zeroing stores can be forwarded to subsequent loads (which can happen if zero-init fields of memory are used, which is not entirely uncommon).

And you can't really avoid the extra store to DRAM. Yes you can handwave about how it can be done while DRAM utilization is low (which is probably actually not trivial), but you can't avoid the energy cost.