By: Etienne Lorrain (etienne_lorrain.delete@this.yahoo.fr), October 6, 2021 2:24 am
Room: Moderated Discussions
Adrian (a.delete@this.acm.org) on October 5, 2021 11:28 pm wrote:
> With many embedded CPUs, using a DMA controller for the larger transfers is certainly better.
As a data point, on an embedded device I wanted to test the DRAM at each boot for bit stuck to high or low or stuck together.
So for 2 GB, I did write 0xFFFFFFFF and then check them, write 0x55555555 and check, write 0xAAAAAAAA and check then write 0x00000000 and check.
Total time less than 1.5 second.
Try that on a CPU...
It did catch once a bad bit going wrong in between factory and costumer.
> With many embedded CPUs, using a DMA controller for the larger transfers is certainly better.
As a data point, on an embedded device I wanted to test the DRAM at each boot for bit stuck to high or low or stuck together.
So for 2 GB, I did write 0xFFFFFFFF and then check them, write 0x55555555 and check, write 0xAAAAAAAA and check then write 0x00000000 and check.
Total time less than 1.5 second.
Try that on a CPU...
It did catch once a bad bit going wrong in between factory and costumer.
