Konrad Schwarz (no.spam.delete@this.no.spam) on October 15, 2021 6:23 am wrote:
> Doug S (foo.delete@this.bar.bar) on September 17, 2021 2:35 pm wrote:
> > nksingh (None.delete@this.none.non) on September 17, 2021 12:23 pm wrote:
> > > Doug S (foo.delete@this.bar.bar) on September 17, 2021 11:35 am wrote:
> > > > And that's even beyond having one of these
> > > > instructions executing in the kernel and an interrupt
> > > > is raised and the interrupt handler starts another. That
> > > > means the state information for in flight instructions
> > > > will have to be saved on the stack - opening another line for potential stack based attacks.
> > > >
> > >
> > > From the exclamation points in the mnemonic description, I assume the state needed
> > > for resume is stored by updating the src, dst, and cnt registers. So it just looks
> > > like a normal instruction to the os with state in the existing registers.
> >
> >
> > I'm not familiar with ARM assembly notation (and haven't written any assembly in any language
> > for many years) so I didn't really notice the exclamation points or understand their significance.
> > Indeed that would make the most sense as the easiest way to handle that detail. Basically the
> > same as if a normal was run using those registers. Thanks for the clarification!
>
> I'd argue this is a hallmark of the CISC vs RISC naming debate:
> a RISC procesor will not use a stack
> for exception handling.


There is additional state stored elsewhere as well. See the recently published instruction descriptions.