By: David Kanter (dkanter.delete@this.realworldtech.com), September 27, 2021 10:04 am
Room: Moderated Discussions
Moritz (better.delete@this.not.tell) on September 27, 2021 4:30 am wrote:
> Mark Roulo (nothanks.delete@this.xxx.com) on September 22, 2021 3:40 pm wrote:
>
> > You can *RUN* it but you don't get the price premium that you
> > get when it is new. TSMC still runs (as an example) 65nm fabs.
> > But the big money is made when the fab is shiny and new.
>
> ATM it would seem that anyone with any fab can find a product that will match the
> process and sell. Profit is more of a productivity question than one of novelty.
>
> > Part
> > of Global Foundry's problem was that it kept being late to
> > each node relative to TSMC and so couldn't charge the new-ness
> > premium.
>
> I see how that makes it unprofitable in a world of progress
> as in decrease in cost per transistor with every new node and over
> time. That is my point, that is not the world we live in anymore.
Actually we still do live in that world. It's just that the cost/transistor improvements are much smaller. It's also possible that EUV will help get back on track.
Generally N+1 node will be better than N for most applications. We've seen some situations where that isn't true (notably Intel desktops and initial 14nm and 10nm), but I suspect if you were to compare N and N+1 within a process flavor (e.g., mobile oriented) it would be strictly better.
> A 320mm^2 die will use less power, but it need not be cheaper or higher performing than a 450mm^2
> die. The fab can run the process longer because the new node is not attracting mid-range or mass
> product. It used to be that only a small die filled with logic could be fit in-between the
> defects but in the age of multicore binning and on-die SRAM monsters rules have changed.
> The trend to stack ICs has not made them smaller, it only increased the manufacturing capacity.
> It must have been obvious that we would need more wafer
> starts as fabs slowed to make more transistors per wafer.
I think cost effective heterogeneous integration will change the rules of the game a lot!
David
> Mark Roulo (nothanks.delete@this.xxx.com) on September 22, 2021 3:40 pm wrote:
>
> > You can *RUN* it but you don't get the price premium that you
> > get when it is new. TSMC still runs (as an example) 65nm fabs.
> > But the big money is made when the fab is shiny and new.
>
> ATM it would seem that anyone with any fab can find a product that will match the
> process and sell. Profit is more of a productivity question than one of novelty.
>
> > Part
> > of Global Foundry's problem was that it kept being late to
> > each node relative to TSMC and so couldn't charge the new-ness
> > premium.
>
> I see how that makes it unprofitable in a world of progress
> as in decrease in cost per transistor with every new node and over
> time. That is my point, that is not the world we live in anymore.
Actually we still do live in that world. It's just that the cost/transistor improvements are much smaller. It's also possible that EUV will help get back on track.
Generally N+1 node will be better than N for most applications. We've seen some situations where that isn't true (notably Intel desktops and initial 14nm and 10nm), but I suspect if you were to compare N and N+1 within a process flavor (e.g., mobile oriented) it would be strictly better.
> A 320mm^2 die will use less power, but it need not be cheaper or higher performing than a 450mm^2
> die. The fab can run the process longer because the new node is not attracting mid-range or mass
> product. It used to be that only a small die filled with logic could be fit in-between the
> defects but in the age of multicore binning and on-die SRAM monsters rules have changed.
> The trend to stack ICs has not made them smaller, it only increased the manufacturing capacity.
> It must have been obvious that we would need more wafer
> starts as fabs slowed to make more transistors per wafer.
I think cost effective heterogeneous integration will change the rules of the game a lot!
David
