By: Doug S (foo.delete@this.bar.bar), September 28, 2021 7:53 am
Room: Moderated Discussions
Moritz (better.delete@this.not.tell) on September 28, 2021 3:04 am wrote:
> David Kanter (dkanter.delete@this.realworldtech.com) on September 27, 2021 10:04 am wrote:
>
> > are much smaller. It's also possible that EUV will help get back on track.
>
> I have doubts. I think it will be a a one time solution or two full
> nodes at best and then we are back to quadruple patterning.
>
> > it would be strictly better.
>
> Yes, but also in cost?
> Will the defect density ever reach the same level as 14nm and earlier for reference?
> Will the gains out-weigh the increase in processing steps and machining costs?
>
> > I think cost effective heterogeneous integration will change the rules of the game a lot!
>
> Let's hope there is economy of scale. There were reasons why it was not done in the past.
> Smaller than PCB integration is moving the production away from low wage low tech manufacturing to more
> centralized, monopolized, sophisticated packaging plants. Not sure how cost effective that is.
>
> Will this lead to a reevaluation of 450mm wafers? In 2017 the industry concluded that 450mm was not
> economical. Is it now or do they want to start more wafers in an increased number of legacy fabs?
> I do not see how the later is economical.
Even if they did 450 mm fabs it would only be for future processes. No one is going to design and sell fab equipment to handle 450 mm wafers in a legacy process.
It has been clear since well before 2017 that 450 mm was never going to happen, and is still clear today. There are too few customers to amortize the cost over. If there was any other way than EUV that wouldn't have happened either, but there was no choice. There is with 450 mm.
EUV isn't just "two nodes and we're back at quadruple patterning". They are using higher NA to reach lower resolutions, last I heard the first such scanners were planned to ship next year. I haven't heard anything about TSMC using double patterning for EUV, but they haven't said much about N2 yet so I guess we'll have to see.
Anyway, there is at least now plenty of learned experience with multiple patterning if/when that's needed again for a few critical layers.
> David Kanter (dkanter.delete@this.realworldtech.com) on September 27, 2021 10:04 am wrote:
>
> > are much smaller. It's also possible that EUV will help get back on track.
>
> I have doubts. I think it will be a a one time solution or two full
> nodes at best and then we are back to quadruple patterning.
>
> > it would be strictly better.
>
> Yes, but also in cost?
> Will the defect density ever reach the same level as 14nm and earlier for reference?
> Will the gains out-weigh the increase in processing steps and machining costs?
>
> > I think cost effective heterogeneous integration will change the rules of the game a lot!
>
> Let's hope there is economy of scale. There were reasons why it was not done in the past.
> Smaller than PCB integration is moving the production away from low wage low tech manufacturing to more
> centralized, monopolized, sophisticated packaging plants. Not sure how cost effective that is.
>
> Will this lead to a reevaluation of 450mm wafers? In 2017 the industry concluded that 450mm was not
> economical. Is it now or do they want to start more wafers in an increased number of legacy fabs?
> I do not see how the later is economical.
Even if they did 450 mm fabs it would only be for future processes. No one is going to design and sell fab equipment to handle 450 mm wafers in a legacy process.
It has been clear since well before 2017 that 450 mm was never going to happen, and is still clear today. There are too few customers to amortize the cost over. If there was any other way than EUV that wouldn't have happened either, but there was no choice. There is with 450 mm.
EUV isn't just "two nodes and we're back at quadruple patterning". They are using higher NA to reach lower resolutions, last I heard the first such scanners were planned to ship next year. I haven't heard anything about TSMC using double patterning for EUV, but they haven't said much about N2 yet so I guess we'll have to see.
Anyway, there is at least now plenty of learned experience with multiple patterning if/when that's needed again for a few critical layers.
