Nios V RISC-V soft cores

By: Gabriele Svelto (gabriele.svelto.delete@this.gmail.com), October 5, 2021 11:28 pm
Room: Moderated Discussions
I just stumbled upon this page. Nios traditionally had its own ISA which was designed with FPGA synthesis in mind so I'm wondering why the change of heart on Intel's part. Maybe RISC-V better tooling offsets any hardware drawbacks? I don't think it's impossible to make good FPGA-optimized RISC-V cores - there are many indeed - but I wonder what are the trade-offs versus an ISA that was meant specifically for FPGAs.
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Nios V RISC-V soft coresGabriele Svelto2021/10/05 11:28 PM
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